CMOS 4-Nit Single Chip Microcomputer Core CPU Manual

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
82 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
XOR r,q Exclusive-OR q-register with r-register
XOR r,q
r ← r ∀ q
1010111 0 r1 r0 q1 q0 AE0H to AEFH
IV
7
Not affected
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Performs an exclusive-OR operation between the contents of the q-register and
the contents of the r-register. The result is stored in the r-register.
XOR A,MY XOR MX,B
A register 0100 1100 1100
B register 1111 1111 1111
Memory (MX) 0111 0111 1000
Memory (MY) 1000 1000 1000
Z flag 0 0 0