Datasheet

AD5541A
Rev. A | Page 15 of 20
UNIPOLAR OUTPUT OPERATION
This DAC is capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 A, and a low offset error. The AD5541A provides a
unipolar output swing ranging from 0 V to V
REF
− 1 LSB.
Figure 31 shows a typical unipolar output voltage circuit. The
code table for this mode of operation is shown in Table 8. The
example includes the ADR421 2.5 V reference and the AD8628
low offset and zero-drift reference buffer.
Table 8. Unipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1111 1111 1111 1111 V
REF
× (65,535/65,536)
1000 0000 0000 0000 V
REF
× (32,768/65,536) = ½ V
REF
0000 0000 0000 0001 V
REF
× (1/65,536)
0000 0000 0000 0000 0 V
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
()
INLVVV
D
V
ZSE
GE
REF
UNIOUT
+++×=
−
16
2
where:
V
OUT−UNI
is the unipolar mode worst-case output.
D is the code loaded to DAC.
V
REF
is the reference voltage applied to the part.
V
GE
is the gain error in volts.
V
ZSE
is the zero-scale error in volts.
INL is the integral nonlinearity in volts.
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±V
REF
output. In a single-supply application, selection of a suitable
op amp may be more difficult because the output swing of the
amplifier does not usually include the negative rail, in this case,
AGND. This can result in some degradation of the specified
performance unless the application does not use codes near zero.
The selected op amp must have a very low offset voltage (the
DAC LSB is 38 V with a 2.5 V reference) to eliminate the need
for output offset trims. Input bias current should also be very
low because the bias current, multiplied by the DAC output
impedance (approximately 6 k), adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, thus increasing the settling time of the output. A
higher 3 dB amplifier bandwidth results in a shorter effective
settling time of the combined DAC and amplifier.
08516-023
V
OUT
V
OUT
V
IN
REF
DGND AGND
V
DD
DIN
SCLK
CS
AD5541A
AD820/
OP196
AD8628
ADR421
+
0.1µF
0.1µF
0.1µF
10µF
UNIPOLAR
OUTPUT
EXTERNAL
OP AMP
5V
5V
SERIAL
INTERFACE
1µF
6
2
4
Figure 31. Unipolar Output