User guide

ManualsBrandsDigilent ManualsHardware410-205P-KIT

1300 Henley Court

Pullman, WA 99163

509.334.6306

www.digilentinc.com

JTAG-HS1™ Programming Cable for Xilinx

FPGAs

Revised January 22, 2015

DOC#: 502-205

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 4

Overview

The joint test action group (JTAG)-HS1 programming cable is a high-speed programming solution for Xilinx field-

programmable gate arrays (FPGAs). It is fully compatible will all Xilinx tools, and can be seamlessly driven from

iMPACT, Chipscope™, and EDK. The HS1 attaches to target boards using Digilent's 6-pin, 100-mil spaced

programming header, or Xilinx's 2x7, 2mm connector (using the included adaptor).

The JTAG-HS1 is powered from a PC's USB port, and will be recognized as a Digilent programming cable when

connected to a PC, whether or not it is attached to the target board. A separate Vdd pin is provided on the HS1 to

supply JTAG signal buffers. The high speed, 24mA, three-state buffers allow target boards to drive the HS1 with

signal voltages from 1.8V to 5V, with bus speeds of up to 30MBit/sec. The HS1's Vdd pin must be tied to the same

voltage supply that drives the JTAG port on the FPGA (see Fig. 1).

JTAG signals are held in high-impedance except when actively driven during programming, so the JTAG bus can be

shared with other devices. The HS1 uses a standard Type-A to Micro-USB cable (included with the HS1) that

attaches to the end of the module opposite the system board connector. The HS1 is small and light, allowing it to

be held firmly in place by the system board connector (see Fig. 2).

The JTAG-HS1.

 Small, complete, all-in-one JTAG programming solution

for Xilinx FPGAs

 Separate Vref drives JTAG/SPI signal voltages; Vref can

be any voltage between 1.8V and 5V.

 High-Speed USB2 port that can drive JTAG/SPI bus at up

to 30Mbit/sec

 JTAG/SPI frequency settable by user

 Compatible with all Xilinx tools

 Uses micro-AB USB2 connector

 SPI programming solution (modes 0 and 2 supported)

 Fully supported by the Adept SDK, allowing custom

JTAG/SPI applications to be created

Features include:

Summary of content (4 pages)

PAGE 1
300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com JTAG-HS1™ Programming Cable for Xilinx® FPGAs Revised January 22, 2015 Overview The joint test action group (JTAG)-HS1 programming cable is a high-speed programming solution for Xilinx fieldprogrammable gate arrays (FPGAs). It is fully compatible will all Xilinx tools, and can be seamlessly driven from iMPACT, Chipscope™, and EDK.
PAGE 2
JTAG-HS1™ Programming Cable for Xilinx® FPGAs Figure 1. Diagram of signal voltages and connections. Figure 2. Xilinx JTAG headers. Software Support In addition to working seamlessly with all Xilinx tools, the HS1 is supported by Digilent's Adept software and the Adept SDK (the SDK can be freely downloaded from Digilent's website). Adept includes a full-featured programming environment, and a set of public APIs that allow user applications to directly drive the JTAG chain.
PAGE 3
JTAG-HS1™ Programming Cable for Xilinx® FPGAs Absolute Maximum Ratings Symbol Parameter Condition Min Max Unit Vdd Operating supply voltage -0.3 4.0 V Vref I/O reference/supply voltage -0.3 6 V VIO Signal Voltage -0.3 6 V IIK,IOK TMS, TCK, TDI, TDO VIO < -0.
PAGE 4
JTAG-HS1™ Programming Cable for Xilinx® FPGAs AC Operating Characteristics HS1 JTAG/SPI signals are driven according to the timing diagram below in Fig. 4. TCK frequencies from 30 MHz to 8 KHz are supported at integer divisions of 30 MHz from 1 to 3750. Common frequencies include 30 MHz, 15 MHz, 10 MHz, and 6 MHz (see Table 1). TCK TCKH TCKL TCK TCD TMS/TDI TSU THD TDO Symbol Parameter Min Max TCK TCK period 33ns 2.185ms TCKH, TCKL TCLK pulse width 20ns 1.