Error Reference Guide

SR870BN4 Error Reference Guide Appendix A: Glossary
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Appendix A: Glossary
Term Definition
ACPI Advanced Configuration and Power Interface.
ANSI American National Standards Institute.
ASCII American Standard Code for Information Interchange. An 8-level code (7 bits plus parity check)
widely used in data processing and data communications systems.
ASIC Application specific integrated circuit.
BERR Bus Error Signal. This signal can be driven by the platform to interrupt the processor that a
platform MCA condition occurred. The processor does not reset any internal state when it sees a
BERR condition. The signal causes a global MCA condition. For further information, see the
Itanium™ Processor Family Error Handling Guide.
BINIT Bus Initialization Signal. This signal can be driven by the processor or platform to indicate a fatal
machine check condition. The processor and platform will reset internal state in order to ensure
the firmware code can be fetched and executed. This signal causes a global MCA condition. For
further information, see the Itanium™ Processor Family Error Handling Guide.
BIOS Basic Input Output System.
BIST Built-In Self Test.
BMC Baseboard Management Controller.
Bridge Circuitry connecting one computer bus to another, allowing an agent on one to access the other.
BSP Boot Strap Processor.
byte 8-bit quantity.
CBC Chassis Bridge Controller. A microcontroller connected to one or more other CBCs. Together they
bridge the IPMB buses of multiple chassis.
CHAP Challenge Handshake Authentication Protocol.
CHS Cylinder- Head-Sector. An older addressing scheme for accessing physical sectors on hard drives
and other storage devices. See LBA.
CMCI Corrected Machine Check Interrupt.
CMOS In terms of this specification, this describes the PC-AT compatible region of battery-backed 128
bytes of memory, which normally resides on the baseboard.
CPEI Corrected Platform Event Interrupt.
CVDR Configuration Values Driven on Reset. A register in the chipset that is accessible by the BMC to
control certain system parameters.
DFT Design for Test. DFT is a set of design rules whose purpose is to improve platform and system
testability.
DMA Direct Memory Access.
DSDT Differentiated System Description Table. An OEM must supply a DSDT to an ACPI-compatible
OS. The DSDT contains the Differentiating Definition Block, which supplies the implementation
and configuration information about the base system.
DTLB Distributed Translation Lookaside Buffer.
DWORD Double Word, a 32-bit quantity.
EEPROM Electrically erasable programmable read-only memory.
ECC Error Correction Code. Refers to a memory system that has extra bit(s) to support limited
detection/correction of memory errors.
EMP Emergency Management Port.
EPS External Product Specification.
FRB Fault Resilient Booting.
FRU Field Replaceable Unit.
GB 1024 MB.