User's Manual
Table Of Contents
- General Description
- More Information
- Contents
- Overview
- Pad Connection Interface
- Recommended Host PCB Layout
- Power Supply Connections and Recommended External Components
- Electrical Specifications
- Environmental Specifications
- Regulatory Information
- Packaging
- Ordering Information
- Acronyms
- Document Conventions
- Document History Page
- Sales, Solutions, and Legal Information
PRELIMINARY
CYBLE-224110-00
Document Number: 002-11264 Rev. *A Page 18 of 43
GPIO
I
DD36
Stop-mode current (V
DDR
)–––nA
T = –40 °C to 85 °C,
V
DDR
= 1.9V to 3.6V
Stop Mode, V
DD
= 3.6 to 5.5V
I
DD37
Stop-mode current (V
DD
)–––nA
T = 25 °C,
V
DD
= 5V
I
DD38
Stop-mode current (V
DDR
)–––nA
T = 25 °C,
V
DDR
= 5V
I
DD39
Stop-mode current (V
DD
) – – – nA T = –40 °C to 85 °C
I
DD40
Stop-mode current (V
DDR
) – – – nA T = –40 °C to 85 °C
Table 12. CYBLE-224110-00 DC Specifications (continued)
Parameter Description Min Typ Max Unit Details/Conditions
Note
4. V
IH
must not exceed V
DD
+ 0.2V.
Table 13. AC Specifications
Parameter Description Min Typ Max Unit Details/Conditions
F
CPU
CPU frequency DC – 48 MHz 1.71V ≤ V
DD
≤ 5.5V
T
SLEEP
Wakeup from Sleep mode – 0 – µs Guaranteed by characterization
T
DEEPSLEEP
Wakeup from Deep-Sleep mode – – 25 µs
24-MHz IMO. Guaranteed by
characterization
T
HIBERNATE
Wakeup from Hibernate mode – – 800 µs Guaranteed by characterization
T
STOP
Wakeup from Stop mode – – 2 ms XRES wakeup
Table 14. GPIO DC Specifications
Parameter Description Min Typ Max Unit Details/Conditions
V
IH
[4]
Input voltage HIGH threshold 0.7 × V
DD
– – V CMOS input
LVTTL input, V
DD
< 2.7V 0.7 × V
DD
– – V –
LVTTL input, V
DD
≥ 2.7V 2.0 – – V –
V
IL
Input voltage LOW threshold – – 0.3 × V
DD
VCMOS input
LVTTL input, V
DD
< 2.7V – – 0.3 × V
DD
V–
LVTTL input, V
DD
≥ 2.7V – – 0.8 V –
V
OH
Output voltage HIGH level V
DD
–0.6 – – V I
OH
= 4 mA at 3.3-V V
DD
Output voltage HIGH level V
DD
–0.5 – – V I
OH
= 1 mA at 1.8-V V
DD
V
OL
Output voltage LOW level – – 0.6 V I
OL
= 8 mA at 3.3-V V
DD
Output voltage LOW level – – 0.6 V I
OL
= 4 mA at 1.8-V V
DD
Output voltage LOW level – – 0.4 V I
OL
= 3 mA at 3.3-V V
DD
R
PULLUP
Pull-up resistor 3.5 5.6 8.5 kΩ –
R
PULLDOWN
Pull-down resistor 3.5 5.6 8.5 kΩ –
I
IL
Input leakage current (absolute value) – – 2 nA 25 °C, V
DD
= 3.3 V
I
IL_CTBM
Input leakage on CTBm input pins – – 4 nA –
C
IN
Input capacitance – – 7 pF –
V
HYSTTL
Input hysteresis LVTTL 25 40 – mV V
DD
> 2.7 V