User's Manual

DescriptionName
Whether the processor fetches cache lines in even/odd pairs
instead of fetching just the required line. This can be one of the
following:
• Disabled—The processor only fetches the required line.
• Enabled— The processor fetches both the required line
and its paired line.
Adjacent Cache Line Prefetcher
Whether the processor uses the DCU IP Prefetch mechanism to
analyze historical cache access patterns and preload the most
relevant lines in the L1 cache. This can be one of the following:
• Disabled—The processor does not try to anticipate cache
read requirements and only fetches explicitly requested
lines.
• Enabled—The DCU prefetcher analyzes the cache read
pattern and prefetches the next line in the cache if it
determines that it may be needed.
DCU Streamer Prefetch
Whether the processor uses the DCU IP Prefetch mechanism to
analyze historical cache access patterns and preload the most
relevant lines in the L1 cache. This can be one of the following:
• Disabled—The processor does not preload any cache data.
• Enabled—The DCU IP prefetcher preloads the L1 cache
with the data it determines to be the most relevant.
DCU IP Prefetcher
Allows processors to increase I/O performance by placing data
from I/O devices directly into the processor cache. This setting
helps to reduce cache misses. This can be one of the following:
• Disabled—Data from I/O devices is not placed directly
into the processor cache.
• Enabled—Data from I/O devices is placed directly into
the processor cache.
Direct Cache Access Support
Cisco UCS C-Series Servers Integrated Management Controller CLI Configuration Guide, Release 1.5
206 OL-28893-01
BIOS Parameters by Server Model
Advanced BIOS Parameters for C220 and C240 Servers