Datasheet

381
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
1t
LHLL
ALE Pulse Width 235 t
CLCL
-15
ns
2t
AVLL
Address Valid A to ALE Low 115 0.5t
CLCL
-10
(1)
3a t
LLAX_ST
Address Hold After ALE Low,
write access
55
3b t
LLAX_LD
Address Hold after ALE Low,
read access
55
4t
AVLLC
Address Valid C to ALE Low 115 0.5t
CLCL
-10
(1)
5t
AVRL
Address Valid to RD Low 235 1.0t
CLCL
-15
6t
AVWL
Address Valid to WR Low 235 1.0t
CLCL
-15
7t
LLWL
ALE Low to WR Low 115 130 0.5t
CLCL
-10
(2)
0.5t
CLCL
+5
(2)
8t
LLRL
ALE Low to RD Low 115 130 0.5t
CLCL
-10
(2)
0.5t
CLCL
+5
(2)
9t
DVRH
Data Setup to RD High 45 45
10 t
RLDV
Read Low to Data Valid 190 1.0t
CLCL
-60
11 t
RHDX
Data Hold After RD High 0 0
12 t
RLRH
RD Pulse Width 235 1.0t
CLCL
-15
13 t
DVWL
Data Setup to WR Low 105 0.5t
CLCL
-20
(1)
14 t
WHDX
Data Hold After WR High 235 1.0t
CLCL
-15
15 t
DVWH
Data Valid to WR High 250 1.0t
CLCL
16 t
WLWH
WR Pulse Width 235 1.0t
CLCL
-15
Table 31-15. External Data Memory Characteristics, 2.7 to 5.5 Volts, No Wait-state (Continued)
Symbol Parameter
4MHz Oscillator Variable Oscillator
UnitMin Max Min Max
Table 31-16. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 0, SRWn0 = 1
Symbol Parameter
4MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 8 MHz
10 t
RLDV
Read Low to Data Valid 440 2.0t
CLCL
-60
ns
12 t
RLRH
RD Pulse Width 485 2.0t
CLCL
-15
15 t
DVWH
Data Valid to WR High 500 2.0t
CLCL
16 t
WLWH
WR Pulse Width 485 2.0t
CLCL
-15