Datasheet

166
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 138.
17.11.33 TIMSK1 – Timer/Counter 1 Interrupt Mask Register
17.11.34 TIMSK3 – Timer/Counter 3 Interrupt Mask Register
17.11.35 TIMSK4 – Timer/Counter 4 Interrupt Mask Register
17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 105) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 105) is executed when the OCFnC Flag, located in
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 105) is executed when the OCFnB Flag, located in
TIFRn, is set.
Bit 76543210
(0x6F)
– –ICIE1– OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value000000 00
Bit 76543210
(0x71)
– –ICIE3– OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value000000 00
Bit 76543210
(0x72)
– –ICIE4– OCIE4C OCIE4B OCIE4A TOIE4 TIMSK4
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value000000 00
Bit 76543210
(0x73)
– –ICIE5– OCIE5C OCIE5B OCIE5A TOIE5 TIMSK5
Read/Write R R R/W RR/W R/W R/W R/W
Initial Value000000 00