Datasheet

113
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
Figure 15-1. Normal pin change interrupt.
15.2 Register Description
15.2.1 EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 15-1 on page 114. Edges on INT3:0 are registered
asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 15-2
on page 114 will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an
interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt
Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt
flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis-
ter before the interrupt is re-enabled.
clk
PCINT(n)
pin_lat
pin_sync
pcint_in_(n)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn
pin_lat
D Q
LE
pcint_setflag
PCIF
clk
clk
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
Bit 76543210
(0x69) ISC31ISC30ISC21ISC20ISC11ISC10ISC01ISC00 EICRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000