Datasheet

4
ATmega128(L)
2467AS–08/01
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega128 provides the following features: 128K bytes of In-System Programma-
ble Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53
general-purpose I/O lines, 32 general purpose working registers, Real Time Counter
(RTC), four flexible timer/counters with compare modes and PWM, 2 USARTs, a byte
oriented 2-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input
stage with programmable gain, programmable Watchdog Timer with internal oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming and six software selectable
power saving modes. The Idle mode stops the CPU while allowing the SRAM,
timer/counters, SPI port, and interrupt system to continue functioning. The Power-down
mode saves the register contents but freezes the oscillator, disabling all other chip func-
tions until the next interrupt or hardware reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction Mode stops the CPU and all I/O modules
except asynchronous timer and ADC, to minimize switching noise during ADC conver-
sions. In Standby mode, the crystal/resonator oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption.
In Extended Standby mode, both the main oscillator and the asynchronous timer con-
tinue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The on-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an on-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is
a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega128 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
ATmega103 and
ATmega128
Compatibility
The ATmega128 is a highly complex microcontroller where the number of I/O locations
supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward
compatibility with the ATmega103, all I/O locations present in ATmega103 have the
same location in ATmega128. Most additional I/O locations are added in an Extended
I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These
location can be reached by using LD/LDS/LDD and ST/STS/STD instruction only, not by
using IN and OUT instruction. The relocation of the internal RAM space may still be a
problem for ATmega103 users. Also, the increased number of interrupt vectors might be
a problem if the code uses absolute addresses. To solve these problems, an
ATmega103 compatibility mode can be selected by programming the fuse M103C. In
this mode, none of the functions in the Extended I/O space are in use, so the internal
RAM is located as in ATmega103. Also, the extended interrupt vectors are removed.