User Manual

18
PRIME / TUF GAMING Intel® 500 Series BIOSマ
CHA IO_Latency_offset / CHB IO_Latency_offset
ョン: [Auto] [0] – [127]
CHA RFR delay / CHB RFR delay
ョン: [Auto] [0] – [127]
Memory Training Algorithms
Early Command Training
ョン: [Auto] [Disabled] [Enabled]
SenseAmp Offset Training
ョン: [Disabled] [Enabled]
Early ReadMPR Timing Centering 2D
ョン: [Disabled] [Enabled]
Read MPR Training
ョン: [Disabled] [Enabled]
Receive Enable Training
ョン: [Disabled] [Enabled]
Jedec Write Leveling
ョン: [Disabled] [Enabled]
LPDDR4 Write DQ DQS Retraining
ョン: [Disabled] [Enabled]
Early Write Time Centering 2D
ョン: [Auto] [Disabled] [Enabled]
Early Read Time Centering 2D
ョン: [Auto] [Disabled] [Enabled]
Write Timing Centering 1D
ョン: [Disabled] [Enabled]
Write Voltage Centering 1D
ョン: [Auto] [Disabled] [Enabled]
Read Timing Centering 1D
ョン: [Auto] [Disabled] [Enabled]
Dimm ODT Training*
DIMMオイ終レーの有効/無効を設定
ョン: [Auto] [Disabled] [Enabled]
は「 Dimm ODT Trainingを[ Disabledするとアクセスでなくなります
Max RTT_WR
ョン: [ODT O󱐯] [120 Ohms]
DIMM RON Training*
ョン: [Auto] [Disabled] [Enabled]