User Guide

AMI BIOS Utility
3-14
cycles on four continues addresses from the DRAM cache. Therefore, it has
four settings to adjust.
The parameter settings are X-4-4-4, X-3-3-3, and X-2-2-2.
Faster DRAMs require shorter wait states. The value of X depends on the
DRAM Lead-off Timing parameter setting. The default is X-4-4-4.
DRAM WRITE BURST TIMING
This parameter adjusts the write wait state between L2 and DRAM cache. The
L2 cache is processed through write-back method and each cache write process
consists of four continuous cache write cycles. Therefore, it has four settings
to adjust.
The parameter settings are X-4-4-4, X-3-3-3, and X-2-2-2.
Faster DRAMs require shorter wait states. The value of X depends on the
DRAM Lead-off Timing parameter setting. The default is X-3-3-3.
FAST RAS TO CAS DELAY (CLOCKS)
This option specifies the wait state between the row address strobe (RAS) and
column address strobe (CAS) signals. The settings are 3 and 2. The default is
3.
DRAM LEAD-OFF TIMING (DLT)
This option specifies the lead-off time before data can be accessed. Some
DRAMs may require a longer delay to access data. The default is
7/6/4/5.
SPECULATIVE LEAD OFF
Enable the parameter to speed up the data read action by presenting the
DRAM controller read request before the controller chip decodes the data to
the final memory target (i.e., cache, DRAM or PCI).
TURN AROUND INSERTION
Enabling this option allows the CPU to insert one turn-around clock cycle to
the MD signals after asserting the MWE signal before enabling the MD
buffers. Set this to Disabled to select the back-to-back DRAM cycles for
asserting MWE signal.