Datasheet

ADV7170/ADV7171
Rev. C | Page 9 of 64
TIMING DIAGRAMS
t
3
t
1
t
6
t
2
t
7
t
5
SDATA
SCLOCK
t
3
t
4
t
8
00221-002
Figure 2. MPU Port Timing Diagram
t
9
t
11
CLOCK
PIXEL INPUT
DATA
t
10
t
12
HSYNC,
FIELD/VSYNC,
BLANK
Cb Y Cr Y Cb Y
HSYNC,
FIELD/VSYNC,
BLANK
t
14
CONTROL
I/PS
CONTROL
O/PS
t
13
00221-003
Figure 3. Pixel and Control Data Timing Diagram
t
16
t
17
t
18
TTXREQ
CLOCK
TTX
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
3 CLOCK
CYCLES
4 CLOCK
CYCLES
00221-004
Figure 4. Teletext Timing Diagram