Datasheet

ADSP-BF561
JTAG Test and Emulation Port Timing
Table 31 and Figure 28 describe JTAG port operations.
Table 31. JTAG Port Timing
Parameter Min Max Unit
Timing Parameters
t
TCK
TCK Period
t
STAP
TDI, TMS Setup Before TCK High
t
HTAP
TDI, TMS Hold After TCK High
t
SSYS
System Inputs Setup Before TCK High
1
t
HSYS
System Inputs Hold After TCK High
1
t
TRSTW
TRST Pulse Width
2
(Measured in TCK Cycles)
Switching Characteristics
t
DTDO
TDO Delay from TCK Low
t
DSYS
System Outputs Delay After TCK Low
3
20
4
4
4
5
4
0
10
12
ns
ns
ns
ns
ns
TCK
ns
ns
1
System Inputs= DATA31–0, ARDY, PF47–0, PPI0CLK, PPI1CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI0, NMI1, BMODE1–0, BR, and PPIxD7–0.
2
50 MHz maximum
3
System Outputs = DATA31–0, ADDR25–2, ABE3–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3–0, PF47–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, and PPIxD7–0.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS
Figure 28. JTAG Port Timing
Rev. E | Page 40 of 64 | September 2009