Datasheet

ADSP-BF561
Serial Peripheral Interface (SPI) Port—
Master Timing
Table 27 and Figure 23 describe SPI port master operations.
Table 27. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
t
HSPIDM
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
t
SDSCIM
SPISELx Low to First SCK Edge
t
SPICHM
Serial Clock High Period
t
SPICLM
Serial Clock Low Period
t
SPICLK
Serial Clock Period
t
HDSM
Last SCK Edge to SPISELx High
t
SPITDM
Sequential Transfer Delay
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
7.5
–1.5
2 × t
SCLK
– 1.5
2 × t
SCLK
– 1.5
2 × t
SCLK
– 1.5
4 × t
SCLK
– 1.5
2 × t
SCLK
– 1.5
2 × t
SCLK
– 1.5
0 6
–1.0 +4.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLAG3–0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
MOSI
(OUT
PUT)
CPHASE = 1
MISO
(INPUT)
MOSI
(OUTPUT)
CPHASE = 0
MISO
(INPUT)
t
SPICHM
t
SDSCIM
t
SPICLM
t
SPICLKM
t
HDSM
t
SPITDM
t
SPICLM
t
SPICHM
MSB
VALID
LSB VALIDMSB VALID
LSB
LSBMSB
MSB
t
DDSPIDM
t
HSPIDM
t
SSPIDM
LSB VALID
t
HDSPIDM
t
HSPIDM
t
HSPIDM
t
SSPIDM
t
SSPIDM
t
DDSPIDM
t
HDSPIDM
Figure 23. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. E | Page 35 of 64 | September 2009