Datasheet

ADSP-BF561
Table 25. Serial Ports—Enable and Three-State
Parameter Min Max Unit
Switching Characteristics
t
DTENE
Data Enable Delay from External TSCLKx
1
t
DDTTE
Data Disable Delay from External TSCLKx
1
t
DTENI
Data Enable Delay from Internal TSCLKx
1
t
DDTTI
Data Disable Delay from Internal TSCLKx
1
0
–2.0
10.0
3.0
ns
ns
ns
ns
1
Referenced to drive edge.
Table 26. External Late Frame Sync
Parameter Min Max Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFSx or External RFSx with MCMEN = 1, MFD = 0
1, 2
t
DTENLFS
Data Enable from Late FS or MCMEN = 1, MFD = 0
1, 2
0
10.0 ns
ns
1
MCMEN = 1, TFSx enable and TFSx valid follow t
DTENLFS
and t
DDTLFSE
.
2
If external RFSx/TFSx setup to RSCLKx/TSCLKx > t
SCLKE
/2, then t
DDTTE / I
and t
DTENE / I
apply; otherwise t
DDTLFSE
and t
DTENLFS
apply.
EXTERNAL RECEIVE FS WITH MCMEN = 1, MFD = 0
DRIVE SAMPLE
2ND BIT
RSCLKx
RFSx
DTx
1ST BIT
DRIVE
t
DDTE/I
t
HDTE/I
t
DDTENFS
t
SFSE/I
t
HFSE/I
t
DDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE SAMPLE
2ND BIT1ST BIT
DRIVE
t
DDTE/I
t
HDTE/I
t
DDTENFS
t
SFSE/I
t
HFSE/I
TSCLKx
TFSx
DTx
t
DDTLFSE
Figure 22. External Late Frame Sync
Rev. E | Page 34 of 64 | September 2009