Datasheet

ADSP-BF561
Serial Ports
Table 23 through Table 26 on Page 34 and Figure 20 on Page 33
through Figure 22 on Page 34 describe Serial Port operations.
Table 23. Serial Ports—External Clock
Parameter Min Max Unit
Timing Requirements
t
SFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
3.0 ns
t
HFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
3.0 ns
t
SDRE
Receive Data Setup Before RSCLKx
1
3.0 ns
t
HDRE
Receive Data Hold After RSCLKx
1
3.0 ns
t
SCLKW
TSCLKx/RSCLKx Width 4.5 ns
t
SCLK
TSCLKx/RSCLKx Period 15.0 ns
t
SUDTE
Start-Up Delay From SPORT Enable To First External TFSx 4.0 TSCLKx
t
SUDRE
Start-Up Delay From SPORT Enable To First External RFSx
Switching Characteristics
4.0 RSCLKx
t
DFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
10.0 ns
t
HOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
0.0 ns
t
DDTE
Transmit Data Delay After TSCLKx
2
10.0 ns
t
HDTE
Transmit Data Hold After TSCLKx
2
0.0 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 24. Serial Ports—Internal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
8.0 ns
t
HFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
–2.0 ns
t
SDRI
Receive Data Setup Before RSCLKx
1
6.0 ns
t
HDRI
Receive Data Hold After RSCLKx
1
0.0 ns
t
SCLKW
TSCLKx/RSCLKx Width 4.5 ns
t
SCLK
TSCLKx/RSCLKx Period 15.0 ns
Switching Characteristics
t
DFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
3.0 ns
t
HOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
–1.0 ns
t
DDTI
Transmit Data Delay After TSCLKx
2
3.0 ns
t
HDTI
Transmit Data Hold After TSCLKx
2
–2.0 ns
t
SCLKIW
TSCLKx/RSCLKx Width 4.5 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Rev. E | Page 32 of 64 | September 2009