Datasheet

Rev. G | Page 36 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
JTAG Test Access Port and Emulation
Table 37. JTAG Test Access Port and Emulation
Parameter Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 ns
t
STAP
TDI, TMS Setup Before TCK High 5 ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
System Inputs Setup Before TCK High
1
7ns
t
HSYS
System Inputs Hold After TCK High
1
8ns
t
TRSTW
TRST Pulse Width 4 × t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 7 ns
t
DSYS
System Outputs Delay After TCK Low
2
10 ns
1
System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
2
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
Figure 27. JTAG Test Access Port and Emulation
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS