Datasheet

ADSP-21161N
Rev. C | Page 47 of 60 | January 2013
Table 34. Serial Ports —– Enable and Three-State
Parameter Min Max Unit
Switching Characteristics
t
DDTEN
Data Enable from External Transmit SCLK
1, 2
4ns
t
DDTTE
Data Disable from External Transmit SCLK
1
10 ns
t
DDTIN
Data Enable from Internal Transmit SCLK
1
0ns
t
DDTTI
Data Disable from Internal Transmit SCLK
1
3ns
1
Referenced to drive edge.
2
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
Table 35. Serial Ports — External Late Frame Sync
Parameter Min Max Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External Transmit FS or External Receive FS with
MCE = 1, MFD = 0
1
13 ns
t
DDTENFS
Data Enable from Late FS or MCE = 1, MFD = 0
1
0.5 ns
1
MCE = 1, Transmit FS enable and Transmit FS valid follow t
DDTLFSE
and t
DDTENFS
.