S DSP Microcomputer ADSP-21160N a SUMMARY High Performance 32-Bit DSP—Applications in Audio, Medical, Military, Graphics, Imaging, and Communication Super Harvard Architecture—Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive, Zero-Overhead I/O Backwards Compatible—Assembly Source Level Compatible with Code for ADSP-2106x DSPs Single-Instruction-Multiple-Data (SIMD) Computational Architecture—Two 32-Bit IEEE Floating-Point Computation Units, Each with a Multiplier, ALU, Shifte
ADSP-21160N KEY FEATURES (continued) IEEE 1149.
ADSP-21160N TABLE OF CONTENTS Power-up Sequencing . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Read—Bus Master . . . . . . . . . . . . . . . .
ADSP-21160N The functional block diagram on Page 1 shows a block diagram of the ADSP-21160N, illustrating the following architectural features: GENERAL DESCRIPTION The ADSP-21160N SHARC DSP is the second iteration of the ADSP-21160. Built in a 0.18 micron CMOS process, it offers higher performance and lower power consumption than its predecessor, the ADSP-21160M.
ADSP-21160N SIMD Computational Engine allows full-speed execution of core, providing looped operations, such as digital filter multiply- accumulates and FFT butterfly processing. The ADSP-21160N contains two computational processing elements that operate as a Single Instruction Multiple Data (SIMD) engine. The processing elements are referred to as PEX and PEY, and each contains an ALU, multiplier, shifter, and register file.
ADSP-21160N PM data, DM addresses, DM data, I/O addresses, and I/O data— are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 64-bit data bus. The lower 32 bits of the external data bus connect to even addresses and the upper 32 bits of the 64 connect to odd addresses. Every access to external memory is based on an address that fetches a 32-bit word, and with the 64-bit bus, two address locations can be accessed at once.
ADSP-21160N commands. Maximum throughput for interprocessor data transfer is 400M bytes/s over the external port. Broadcast writes allow simultaneous transmission of data to all ADSP-21160Ns and can be used to implement reflective semaphores. ADDRESS DATA DATA RESET ADDRESS CLKIN CONTROL ADSP-21160 #3 CONTROL ADSP-21160 #6 ADSP-21160 #5 ADSP-21160 #4 Six link ports provide for a second method of multiprocessing communications. Each link port can support communications to another ADSP-21160N.
ADSP-21160N Link Ports Power Supplies The ADSP-21160N features six 8-bit link ports that provide additional I/O capabilities. With the capability of running at 100 MHz rates, each link port can support 80M bytes/s. Link port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate independently and simultaneously.
ADSP-21160N Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. • View mixed C/C++ and assembly code (interleaved source and object information) Analog Devices DSP emulators use the IEEE 1149.
ADSP-21160N Tie or pull unused inputs to VDD or GND, except for the following: • ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT (ID2–0 = 00x) (Note: These pins have a logic-level hold circuit enabled on the ADSP-21160N DSP with ID2–0 = 00x.) • PA, ACK, MS3–0, RDx, WRx, CIF, DMARx, DMAGx (ID2–0 = 00x) (Note: These pins have a pull-up enabled on the ADSP-21160N DSP with ID2–0 = 00x.
ADSP-21160N Table 2. Pin Function Descriptions (continued) Pin Type Function PAGE O/T BRST I/O/T ACK I/O/S SBTS I/S IRQ2–0 I/A FLAG3–0 I/O/A TIMEXP O HBR I/A HBG I/O CS I/A REDY O (O/D) DMAR1 I/A DRAM Page Boundary. The ADSP-21160N asserts this pin to an external DRAM controller, to signal that an external DRAM page boundary has been crossed. DRAM page size must be defined in the ADSP-21160N’s memory control register (WAIT).
ADSP-21160N Table 2. Pin Function Descriptions (continued) Pin Type Function DMAR2 I/A ID2–0 I DMAG1 O/T DMAG2 O/T BR6–1 I/O/S RPBA I/S PA I/O/T DTx DRx TCLKx RCLKx TFSx RFSx LxDAT7–0 O I I/O I/O I/O I/O I/O LxCLK I/O LxACK I/O EBOOT I LBOOT I BMS I/O/T CLKIN I DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has a 20 kΩ internal pull-up resistor that is enabled on the ADSP21160N with ID2–0 = 00x. Multiprocessing ID.
ADSP-21160N Table 2. Pin Function Descriptions (continued) Pin Type Function CLK_CFG3–0 I CLKOUT O/T RESET I/A TCK TMS I I/S TDI I/S TDO TRST O I/A EMU O (O/D) CIF O/T VDDINT P VDDEXT AVDD P P AGND GND NC G G Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal to n CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
ADSP-21160N SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter VDDINT AVDD VDDEXT TCASE VIH1 VIH2 VIL Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage Case Operating Temperature1 High Level Input Voltage,2 @ VDDEXT =Max High Level Input Voltage,3 @ VDDEXT =Max Low Level Input Voltage,2, 3 @ VDDEXT =Min C Grade K Grade Min Max Min Max Unit 1.8 1.8 3.13 – 40 2.0 2.0 –0.5 2.0 2.0 3.47 +100 VDDEXT +0.5 VDDEXT +0.5 +0.8 1.8 1.8 3.13 0 2.0 2.0 –0.5 2.
ADSP-21160N 6 Applies to CLKIN only. Applies to all pins with keeper latches: ADDR31–0, DATA63–0, PAGE, BRST, CLKOUT. 8 Current required to switch from kept high to low or from kept low to high. 9 Characterized, but not tested. 10 Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO. 11 Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.
ADSP-21160N TIMING SPECIFICATIONS The ADSP-21160N’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock (the clock source for the external port logic and I/O pads).
ADSP-21160N Table 4.
ADSP-21160N Clock Input For Clock Input, see Table 5 and Figure 8. Table 5. Clock Input 100 MHz Parameter Timing Requirements CLKIN Period tCK tCKL CLKIN Width Low tCKH CLKIN Width High CLKIN Rise/Fall (0.4 V–2.0 V) tCKRF tCCLK Core Clock Period Min Max Unit 20 7.5 7.5 80 40 40 3 30 ns ns ns ns ns 10 tCK CLKIN tCKH tCKL Figure 8. Clock Input Reset For Reset, see Table 6 and Figure 9. Table 6.
ADSP-21160N Interrupts For Interrupts, see Table 7 and Figure 10. Table 7. Interrupts 1 2 Parameter Min Timing Requirements tSIR IRQ2–0 Setup Before CLKIN High1 tHIR IRQ2–0 Hold After CLKIN High1 tIPW IRQ2–0 Pulsewidth2 6 0 2+tCK Max Unit ns ns ns Only required for IRQx recognition in the following cycle. Applies only if tSIR and tHIR requirements are not met. CLKIN tSIR tHIR IRQ2–0 tIPW Figure 10. Interrupts Timer For Timer, see Table 8 and Figure 11. Table 8.
ADSP-21160N Flags For Flags, see Table 9 and Figure 12. Table 9.
ADSP-21160N Memory Read—Bus Master apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing parameters only applies to asynchronous access mode. See Table 10 and Figure 13. Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications Table 10.
ADSP-21160N apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing parameters only applies to asynchronous access mode. Memory Write—Bus Master See Table 11 and Figure 14. Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications Table 11.
ADSP-21160N Synchronous Read/Write—Bus Master See Table 12 and Figure 15. Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-21160N (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read–Bus Master on Page 21 and Memory Write–Bus Master on Page 22).
ADSP-21160N CLKIN tCKOP tCKWH tDCKOO tCKWL CLKOUT tDADDO tHADDO ADDRESS MSx, BRST, CIF tDPGO PAGE tHACKC tSACKC ACK (IN) tDACKMO tACKMTR ACK (OUT) READ CYCLE tDRWL tDRDO RDx tSSDATI tHSDATI DATA (IN) WRITE CYCLE tDWRO tDRWL WRx tHDATO tDDATO DATA (OUT) Figure 15. Synchronous Read/Write—Bus Master –24– REV.
ADSP-21160N Synchronous Read/Write—Bus Slave See Table 13 and Figure 16. Use these specifications for ADSP21160N bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements. Table 13.
ADSP-21160N Multiprocessor Bus Request and Host Bus Request See Table 14 and Figure 17. Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ns (BRx) or a host processor, both synchronous and asynchronous (HBR, HBG). Table 14.
ADSP-21160N CLKIN t SHBRI tHHBRI HBR tDHBGO tHHBGO HBG (OUT) tDBRO tHBRO BRx (OUT) t TRP AS tDPASO PA (OUT) (SLAVE) tPATR tDPAMO PA (OUT) (MASTER) tS HBG I tHHBG I HBG (IN) t SBRI tHBRI BRx, PA (IN) tSRP BAI tHRPBAI RPBA HBR CS tT RDY HG t DRDYCS REDY (O/D) tARDY TR REDY (A/D) t HBGRCSV HBG (OUT) RDx WRx CS O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 17. Multiprocessor Bus Request and Host Bus Request REV.
ADSP-21160N Asynchronous Read/Write—Host to ADSP-21160N Use these specifications (Table 15, Table 16, Figure 18, and Figure 19) for asynchronous host processor accesses of an ADSP-21160N, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-21160N, the host can drive the RDx and WRx pins to access the ADSP-21160N’s internal memory or IOP registers. HBR and HBG are assumed low for this timing. Table 15.
ADSP-21160N READ CYCLE ADDRESS/ CS tH AD R D H tS AD R D L tWR WH RDx tH D A R WH D ATA (OUT) tSD A TR DY tD RD YRD L tD R D HR D Y t RD Y PR D REDY (O/ D) REDY (A/D) Figure 18. Asynchronous Read—Host to ADSP-21160N WRITE CYCLE ADDRESS tSA D WR H tS C SWR L tH AD W RH t HC S WR H CS tWWR L tWR WH WRx tH D A TWH tSD A TWH DATA (I N) tD R D YW RL tR D YP WR tD WR H R DY REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/ D = ACTIVE DRIVE Figure 19.
ADSP-21160N Three-State Timing—Bus Master, Bus Slave See Table 17 and Figure 20. These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. Table 17.
ADSP-21160N CLKIN tSTSCK tHTSCK SBTS tMIENA, tMIENS, tMIENHG tMITRA, tMITRS, tMITRHG MEMORY INTERFACE tDATTR tDATEN DATA tACKTR tACKEN ACK tCDCEN tCDCTR CLKOUT tATRHBG tSTRHBG tPTRHBG tBTRHBG HBG tMENHBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RDx, WRx, MSx, PAGE, DMAGx. BMS (IN EPROM BOOT MODE) Figure 20. Three-State Timing—Bus Master, Bus Slave REV.
ADSP-21160N Paced Master mode, the data transfer is controlled by ADDR31–0, RDx, WRx, MS3–0, and ACK (not DMAG). For Paced Master mode, the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for ADDR31–0, RDx, WRx, MS3–0, PAGE, DATA63–0, and ACK also apply. DMA Handshake See Table 18 and Figure 21. These specifications describe the three DMA handshake modes. In all three modes, DMARx is used to initiate transfers.
ADSP-21160N CLKIN t SDRC t DMARLL t SDRC t WDR t DMARH DMARx t HDGC t DDGL t W DGL tW DGH DMAGx TRANSFERS BETWEEN ADSP-2116X INTERNAL MEMORY AND EXTERNAL DEVICE tDATRDGH t VDATDGH DATA (FROM ADSP-2116X TO EXTERNAL DRIVE) tDATDRH t SDATDG L tHDATIDG DATA (FROM EXTERNAL DRIVE TO ADSP-2116X) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTER NAL MEMORY*(EXTERNAL HANDSHAKE MODE) t DGW RL t DGW RH t DGW RR WRx (EXTERNAL DEVICE TO EXTERNAL MEMORY) tDG RDR t DGRDL RDx (EXTERNAL MEMOR Y TO EXTERNAL DEVIC
ADSP-21160N Link Ports —Receive, Transmit For Link Ports, see Table 19, Table 20, Figure 22, and Figure 23. Calculation of link receiver data setup and hold, relative to link clock, is required to determine the maximum allowable skew that can be introduced in the transmission path, between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA, relative to LCLK (setup skew = tLCLKTWH minimum – tDLDCH – tSLDCL).
ADSP-21160N TRANSMIT tLCLKTWH tLCLKTWL LAST NIBBLE/BYTE TRANSMITTED FIRST NIBBLE/BYTE TRANSMITTED LCLK INACTIVE (HIGH) LCLK tDLDCH tHLDCH LDAT(7:0) OUT tSLACH tHLACH LACK (IN) THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. Figure 23. Link Ports—Transmit REV.
ADSP-21160N Serial Ports For Serial Ports, see Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Figure 24, and Figure 25. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 21.
ADSP-21160N Table 26. Serial Ports—Internal Clock Parameter Min Switching Characteristics TFS Delay After TCLK (Internally Generated TFS)1 tDFSI tHOFSI TFS Hold After TCLK (Internally Generated TFS)1 Transmit Data Delay After TCLK1 tDDTI tHDTI Transmit Data Hold After TCLK1 tSCLKIW TCLK/RCLK Width 1 Max Unit 4.5 0 0.5tSCLK –1.5 0.5tSCLK +1.5 ns ns ns ns ns Min Max Unit 13 ns –1.5 7.5 Referenced to drive edge. Table 27.
ADSP-21160N DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE DATA RECEIVE— EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW RCLK SAMPLE EDGE tSCLKW RCLK tDFSE tDFSE tSFSI tHOFSE tHOFSE tHFSI RFS tSFSE tHFSE tSDRE tHDRE RFS tSDRI tHDRI DR DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
ADSP-21160N JTAG Test Access Port and Emulation For JTAG Test Access Port and Emulation, see Table 28 and Figure 26. Table 28.
ADSP-21160N Output Drive Currents % Peak × I DD-INPEAK Figure 27 shows typical I–V characteristics for the output drivers of the ADSP-21160N. The curves represent the current drive capability of the output drivers as a function of output voltage. % High × I DD-INHIGH % Low × I DD-INLOW + % Idle × I DD-IDLE ----------------------------------------------------I DDINT 80 VDDEXT = 3.47V, –45°C VDDEXT = 3.
ADSP-21160N where: Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. • PEXT is from Table 30 • PINT is IDDINT × 1.9 V, using the calculation IDDINT listed in Power Dissipation on Page 40 • PPLL is AIDD × 1.
ADSP-21160N Capacitive Loading Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 29). Figure 31 and Figure 32 show how output rise time varies with capacitance. Figure 33 graphically shows how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 41.) The graphs of Figure 31, Figure 32, and Figure 33 may not be linear outside the ranges shown.
ADSP-21160N 400-BALL METRIC PBGA PIN CONFIGURATIONS Table 32 lists the pin assignments for the PBGA package, and the pin configurations diagram in Figure 34 shows the pin assignment summary. Table 32. 400-Ball Metric PBGA Pin Assignments Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
ADSP-21160N Table 32. 400-Ball Metric PBGA Pin Assignments (continued) Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
ADSP-21160N Table 32. 400-Ball Metric PBGA Pin Assignments (continued) Pin Name Pin No. L4DAT[0] U18 L4DAT[1] U19 L4DAT[2] U20 Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
ADSP-21160N OUTLINE DIMENSIONS The ADSP-21160N comes in a 27 mm 27 mm, 400-ball Metric PBGA package with 20 rows of balls. 400-Ball Metric PBGA (B-400) 27.20 27.00 SQ 26.80 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y 24.13 BSC SQ 1.27 BSC BALL PITCH BOTTOM VIEW TOP VIEW 2.49 2.32 2.15 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-034-BAL-2. 2. CENTER FIGURES ARE NOMINAL DIMENSIONS. 3.
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