Datasheet

ManualsBrandsAnalog Devices ManualsEmbedded Processors & ControllersLogic IC Voltage-Level Translator TSSOP-

Low Voltage, 1.15 V to 5.5 V, 4-Channel,

Bidirectional Logic Level Translator

Data Sheet

ADG3304

Rev. E Document Feedback

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FEATURES

Bidirectional level translation

Operates from 1.15 V to 5.5 V

Low quiescent current < 5 µA

No direction pin

Qualified for automotive applications

APPLICATIONS

SPI, MICROWIRE level translation

Low voltage ASIC level translation

Smart card readers

Cell phones and cell phone cradles

Portable communications devices

Telecommunications equipment

Network switches and routers

Storage systems (SAN/NAS)

Computing/server applications

GPS

Portable POS systems

Low cost serial interfaces

FUNCTIONAL BLOCK DIAGRAM

GND

CCY

CCA

04860-001

Figure 1.

GENERAL DESCRIPTION

The ADG3304 is a bidirectional logic level translator that con-

tains four bidirectional channels. It can be used in multivoltage

digital system applications, such as data transfer, between a low

voltage digital signal processing controller and a higher voltage

device using SPI and MICROWIRE interfaces. The internal

architecture allows the device to perform bidirectional logic

level translation without an additional signal to set the direction

in which the translation takes place.

The voltage applied to V

CCA

sets the logic levels on the A side of

the device, while V

CCY

sets the levels on the Y side. For proper

operation, V

CCA

must always be less than V

CCY

. The V

CCA

-com-

patible logic signals applied to the A side of the device appear as

CCY

-compatible levels on the Y side. Similarly, V

CCY

-compatible

logic levels applied to the Y side of the device appear as V

CCA

compatible logic levels on the A side.

The enable pin (EN) provides three-state operation on both the

A side and the Y side pins. When the EN pin is pulled low, the

terminals on both sides of the device are in the high impedance

state. The EN pin is referred to the V

CCA

supply voltage and

driven high for normal operation.

The ADG3304 is available in compact 14-lead TSSOP, 12-ball

WLCSP, and 20-lead LFCSP. It is guaranteed to operate over

the 1.15 V to 5.5 V supply voltage range.

PRODUCT HIGHLIGHTS

1. Bidirectional level translation.

2. Fully guaranteed over the 1.15 V to 5.5 V supply range.

3. No direction pin.

4. Available in 14-lead TSSOP, 12-ball WLCSP, and 20-lead

LFCSP.

Downloaded from Arrow.com.

Summary of content (21 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM Bidirectional level translation Operates from 1.15 V to 5.
PAGE 2
ADG3304 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ....................................................................................... 1 Level Translator Architecture ................................................... 17 Functional Block Diagram ........................................................
PAGE 3
Data Sheet ADG3304 SPECIFICATIONS VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V, TA = 25°C. All specifications TMIN to TMAX, unless otherwise noted. Table 1. B Version 1 Typ Max Parameter LOGIC INPUTS/OUTPUTS A Side Input High Voltage 2 Symbol Test Conditions/Comments Min VIHA VCCA × 0.88 VCCA × 0.72 1.7 2.2 VCCA × 0.7 Input Low Voltage2 VILA VCCA = 1.2 V + 0.1 V/−0.05 V VCCA = 1.8 V ± 0.15 V VCCA = 2.5 V ± 0.2 V VCCA = 3.3 V ± 0.3 V VCCA = 5 V ± 0.5 V VCCA = 1.2 V + 0.1 V/−0.
PAGE 4
ADG3304 Parameter SWITCHING CHARACTERISTICS2 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation Propagation Delay Data Sheet Symbol Test Conditions/Comments Min B Version 1 Typ Max Unit RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y 6 10 ns Rise Time tR, A→Y 2 3.5 ns Fall Time tF, A→Y 2 3.
PAGE 5
Data Sheet Parameter 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A→Y Translation Propagation Delay ADG3304 Symbol B Version 1 Typ Max Unit RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y 12 25 ns tR, A→Y 7 12 ns Fall Time tF, A→Y 3 5 Maximum Data Rate DMAX, A→Y Channel-to-Channel Skew tSKEW, A→Y Part-to-Part Skew tPPSKEW, A→Y 25 ns Mbps 2 5 ns 15 ns RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A 14 35 ns Rise Time tR, Y→A 5 16 ns Fall Time tF, Y→A 2.5 6.
PAGE 6
ADG3304 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCCA to GND VCCY to GND Digital Inputs (A) Digital Inputs (Y) EN to GND Operating Temperature Range Storage Temperature Range Junction Temperature θJA Thermal Impedance (4-Layer Board) 14-Lead TSSOP 12-Ball WLCSP 20-Lead LFCSP Lead Temperature, Soldering Rating −0.3 V to +7 V VCCA to +7 V −0.3 V to (VCCA + 0.3 V) −0.3 V to (VCCY + 0.3 V) −0.
PAGE 7
Data Sheet ADG3304 1 14 A1 2 13 Y1 A2 3 ADG3304 12 Y2 A3 4 TOP VIEW (Not to Scale) 11 Y3 A4 5 NC 6 9 NC GND 7 8 EN 20 19 18 17 16 VCCY NC A2 A3 A4 NC 04860-002 NC = NO CONNECT ADG3304 TOP VIEW (Not to Scale) 15 14 13 12 11 NC Y2 Y3 Y4 NC NC 6 NC 7 GND 8 EN 9 NC 10 10 Y4 1 2 3 4 5 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE CAN BE TIED TO GND OR LEFT FLOATING. DO NOT TIE IT TO VCCA OR VCCY .
PAGE 8
ADG3304 Data Sheet BALL A1 INDICATOR 1 2 3 Y1 VCCY A1 Y2 VCCA A2 Y3 EN A3 Y4 GND A4 A B D 04860-003 C TOP VIEW (BALLS AT THE BOTTOM) Not to Scale Figure 4. 12-Ball WLCSP Pin Configuration Table 4. 12-Ball WLCSP Pin Function Descriptions Pin No. A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 Mnemonic Y1 Y2 Y3 Y4 VCCY VCCA EN GND A1 A2 A3 A4 Description Input/Output Y1. Referenced to VCCY. Input/Output Y2. Referenced to VCCY. Input/Output Y3. Referenced to VCCY. Input/Output Y4.
PAGE 9
Data Sheet ADG3304 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 1.0 TA = 25°C 1 CHANNEL 0.9 CL = 50pF 2.5 0.8 VCCA = 3.3V, VCCY = 5V 0.7 2.0 0.6 ICCY (mA) ICCA (mA) TA = 25°C 1 CHANNEL CL = 15pF 0.5 0.4 VCCA = 1.8V, VCCY = 3.3V 0.3 VCCA = 3.3V, VCCY = 5V 1.5 1.0 VCCA = 1.8V, VCCY = 3.3V 0.2 0.5 0.1 5 10 15 35 30 20 25 DATA RATE (Mbps) 40 45 50 VCCA = 1.2V, VCCY = 1.8V 0 0 15 20 25 30 35 40 50 45 Figure 8. ICCY vs. Data Rate (Y→A Level Translation) 1.
PAGE 10
ADG3304 9 Data Sheet 7 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 8 7 TA = 25°C 1 CHANNEL 6 VCCA = 3.3V VCCY = 5V 50Mbps 50Mbps 5 ICCA (mA) ICCY (mA) 6 5 30Mbps 4 4 30Mbps 3 20Mbps 3 20Mbps 2 2 10Mbps 10Mbps 1 1 33 43 53 CAPACITIVE LOAD (pF) 63 0 04865-016 23 73 13 5.0 4.0 53 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 3.5 VCCA = 1.2V, VCCY = 1.8V 7 50Mbps 3.0 RISE TIME (ns) ICCA (mA) 33 43 CAPACITIVE LOAD (pF) Figure 14.
PAGE 11
Data Sheet ADG3304 12 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 VCCA = 1.2V, VCCY = 1.8V 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 2 8 6 VCCA = 1.8V, VCCY = 3.3V 4 2 1 VCCA = 3.3V, VCCY = 5V 23 28 33 38 43 48 53 CAPACITIVE LOAD (pF) 0 13 04860-025 18 23 33 43 53 63 73 CAPACITIVE LOAD (pF) 04860-028 VCCA = 3.3V, VCCY = 5V 0 13 Figure 20. Propagation Delay (tPHL) vs. Capacitive Load at Pin Y (A→Y Level Translation) Figure 17. Rise Time vs.
PAGE 12
ADG3304 Data Sheet TA = 25°C DATA RATE = 25Mbps CL = 50pF 1 CHANNEL 400mV/DIV Figure 26. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps) Figure 23. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps) 5ns/DIV TA = 25°C DATA RATE = 50Mbps CL = 50pF 1 CHANNEL 1V/DIV Figure 27. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps) Figure 24. Eye Diagram at A Output (1.8 V to 1.
PAGE 13
Data Sheet ADG3304 TEST CIRCUITS EN VCCA ADG3304 VCCY 0.1µF 0.1µF EN ADG3304 VCCA A VCCY Y 0.1µF 0.1µF K2 K1 GND IOH A K Y A IOL Figure 29. VOH/VOL Voltages at Pin A EN ADG3304 VCCA Figure 32. Three-State Leakage Current at Pin Y VCCY 0.1µF 0.1µF VCCA K2 ADG3304 VCCY 0.1µF Y A 04860-046 04860-043 GND 0.1µF K1 Y A GND A IOL 04860-044 EN ADG3304 GND Figure 33. EN Pin Leakage Current Figure 30.
PAGE 14
ADG3304 Data Sheet EN VCCA ADG3304 VCCY A Y CAPACITANCE METER 04860-049 GND Figure 35. Capacitance at Pin Y A→Y DIRECTION VCCA 0.1µF VCCY ADG3304 + 10µF + 10µF 0.1µF 1MΩ A VA K1 Y VY K2 50pF 1MΩ SIGNAL SOURCE EN Z0 = 50Ω RS GND VEN 50Ω RT 50Ω Y→A DIRECTION VCCA 0.1µF VCCY ADG3304 + 10µF + 10µF 0.
PAGE 15
Data Sheet ADG3304 EN VCCY ADG3304 VCCA SIGNAL SOURCE RS 0.1µF Z0 = 50Ω V A 50Ω EN + 10µF 0.1µF + 10µF VCCA Y RT 50Ω VA VY + 10µF 0.1µF SIGNAL SOURCE A Y VY Z0 = 50Ω RS 50Ω RT 50Ω 15pF 50pF VCCY + 10µF 0.1µF A ADG3304 GND GND VY VA 50% tP,A→Y tP,A→Y VA VY tF,A→Y tR,A→Y 04860-051 90% 50% 10% Figure 37. Switching Characteristics (A→Y Level Translation) Rev. E | Page 15 of 21 Downloaded from Arrow.com. tP,Y→A tP,Y→A 90% 50% 10% tF,Y→A tR,Y→A Figure 38.
PAGE 16
ADG3304 Data Sheet TERMINOLOGY VIHA Logic input high voltage at Pin A1 to Pin A4. TF, A→Y Fall time when translating logic levels in the A→Y direction. VILA Logic input low voltage at Pin A1 to Pin A4. DMAX, A→Y Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions specified in Table 1. VOHA Logic output high voltage at Pin A1 to Pin A4. VOLA Logic output low voltage at Pin A1 to Pin A4. CA Capacitance measured at Pin A1 to Pin A4 (EN = 0).
PAGE 17
Data Sheet ADG3304 THEORY OF OPERATION The ADG3304 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each side of the device. When driving the A pins, the device translates the VCCAcompatible logic levels to VCCY-compatible logic levels available at the Y pins.
PAGE 18
ADG3304 Data Sheet DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the VCCA and VCCY supply voltage combination and the load capacitance. It is given by the maximum frequency of a square wave that can be applied to the device, which meets the VOH and VOL levels at the output and does not exceed the maximum junction temperature (see the Absolute Maximum Ratings section).
PAGE 19
Data Sheet ADG3304 APPLICATIONS INFORMATION The ADG3304 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the A pins, and the higher voltage logic signals are connected to the Y pins. The ADG3304 can provide level translation in both directions from A→Y or Y→A on all four channels, eliminating the need for a level translator IC for each direction.
PAGE 20
ADG3304 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 0.30 0.19 0.75 0.60 0.45 8° 0° SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 42. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 1.670 1.610 1.550 BOTTOM VIEW (BALL SIDE UP) 3 2 1 A BALL A1 IDENTIFIER 2.070 2.010 1.950 1.50 REF B C D 0.
PAGE 21
Data Sheet ADG3304 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. 08-16-2010-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 44.