Datasheet

Data Sheet ADF41020
Rev. A | Page 13 of 16
THE FUNCTION LATCH
With C2 and C1 set to 1 and 0, respectively, the on-chip
function latch is programmed. Figure 17 shows the input
data format for programming the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this is 1, the R counter
and the N (A, B) counter is reset. For normal operation, this bit
should be 0. When powering up, disable the F1 bit (set to 0).
The N counter then resumes counting in close alignment with
the R counter. (The maximum error is one prescaler cycle).
Power-Down
Bit DB3 (PD1) provides a software power-down mode to reduce
the overall current drawn by the device. It is enabled by the CE
pin. When the CE pin is low, the device is immediately disabled
regardless of the state of PD1.
In the programmed software power-down, the device powers
down immediately after latching 1 into the PD1 bit. PD2 is a
reserved bit and should be cleared to 0.
When a power-down is activated, the following events occur:
• All active dc current paths in the main synthesizer section
are removed. However, the RF divide-by-4 prescaler
remains active.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital clock detect circuitry is reset.
• The RF
IN
input is debiased.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF41020. Figure 17 shows the truth table.
Fast Lock Enable Bit
Bit DB9 (F4) of the function latch is the fast lock enable bit.
When this bit is 1, fast lock is enabled.
Fast Lock Mode Bit
Bit DB10 (F5)of the function latch is the fast lock mode bit.
When fast lock is enabled, this bit determines which fast lock
mode is used. If the fast lock mode bit is 0, then Fast Lock
Mode 1 is selected; and if the fast lock mode bit is 1, then Fast
Lock Mode 2 is selected.
Fast Lock Mode 1
The charge pump current is switched to the contents of Current
Setting 2. The device enters fast lock when 1 is written to the CP
gain bit in the N (A, B) counter latch. The device exits fast lock
when 0 is written to the CP gain bit in the N (A, B) counter latch.
Fast Lock Mode 2
The charge pump current is switched to the contents of Current
Setting 2. The device enters fast lock when 1 is written to the
CP gain bit in the N (A, B) counter latch. The device exits fast
lock under the control of the timer counter. After the timeout
period, which is determined by the value in TC4 to TC1, the CP
gain bit in the N (A, B) counter latch is automatically reset to 0,
and the device reverts to normal mode instead of fast lock. See
Figure 17 for the timeout periods.
Timer Counter Control
The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is used when the system is dynamic and in a state of
change (that is, when a new output frequency is programmed).
The normal sequence of events follows.
The user initially decides what the preferred charge pump
currents are going to be. For example, the choice may be
0.85 mA as Current Setting 1 and 1.7 mA as Current Setting 2.
Simultaneously, the decision must be made as to how long the
secondary current stays active before reverting to the primary
current. This is controlled by the timer counter control bits,
DB14 to DB11 (TC4 to TC1), in the function latch. The truth
table is given in Figure 17
.
To program a new output frequency, simply program the N (A, B)
counter latch with new values for A and B. Simultaneously, the
CP gain bit can be set to 1, which sets the charge pump with the
value in CPI6 to CPI4 for a period of time determined by TC4
to TC1. When this time is up, the charge pump current reverts
to the value set by CPI3 to CPI1. At the same time, the CP gain
bit in the N (A, B) counter latch is reset to 0 and is ready for the
next time the user wishes to change the frequency.
Note that there is an enable feature on the timer counter. It is
enabled when Fast Lock Mode 2 is chosen by setting the fast
lock mode bit (DB10) in the function latch to 1.
Charge Pump Currents
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Figure 17.
Prescaler Value
P2 and P1 in the function latch set the programmable P
prescaler value. The P value should be chosen so that the
prescaler output frequency is always less than or equal to
350 MHz.
PD Polarity
Bit DB7 (F2) sets the phase detector polarity bit. See Figure 17.