Datasheet

ManualsBrandsANALOG DEVICES ManualsLinear ICsADCLK946BCPZ

Six LVPECL Outputs,

SiGe Clock Fanout Buffer

ADCLK946

Rev. A

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FEATURES

4.8 GHz operating frequency

75 fs rms broadband random jitter

On-chip input terminations

3.3 V power supply

APPLICATIONS

Low jitter clock distribution

Clock and data signal restoration

Level translation

Wireless communications

Wired communications

Medical and industrial imaging

ATE and high performance instrumentation

GENERAL DESCRIPTION

The ADCLK946 is an ultrafast clock fanout buffer fabricated on

the Analog Devices, Inc., proprietary XFCB3 silicon germanium

(SiGe) bipolar process. This device is designed for high speed

applications requiring low jitter.

The device has a differential input equipped with center-tapped,

differential, 100 Ω on-chip termination resistors. The input accepts

dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and

ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A V

REF

is available for biasing ac-coupled inputs.

The ADCLK946 features six full-swing emitter-coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias V

to the positive supply and V

to ground. For ECL

operation, bias V

to ground and V

to the negative supply.

The ECL output stages are designed to directly drive 800 mV

each side into 50 Ω terminated to V

− 2 V for a total differen-

tial output swing of 1.6 V.

The ADCLK946 is available in a 24-lead LFCSP and is specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

LVPECL

CLK

REF

CLK

ADCLK946

REFERENCE

08053-001

Figure 1.

Summary of content (12 pages)

PAGE 1
Six LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK946 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.
PAGE 2
ADCLK946 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Performance ...................................................................5 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................6 General Description .........................................................................
PAGE 3
ADCLK946 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical (typ) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted. Table 1.
PAGE 4
ADCLK946 Table 3. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 2 Symbol Min VCC − VEE 2.97 IVEE IVCC PSRVCC PSRVCC Typ 90 245 <3 28 Change in tPD per change in VCC. Change in output swing per change in VCC. Rev. A | Page 4 of 12 Max Unit Test Conditions/Comments 3.63 V 115 275 mA mA ps/V dB 3.3 V + 10% Static VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.
PAGE 5
ADCLK946 ABSOLUTE MAXIMUM RATINGS DETERMINING JUNCTION TEMPERATURE Table 4. Parameter Supply Voltage VCC − VEE Input Voltage CLK, CLK CLK, CLK to VT Pin (CML, LVPECL Termination) CLK to CLK Input Termination, VT to CLK, CLK Maximum Voltage on Output Pins Maximum Output Current Voltage Reference (VREF) Operating Temperature Range Ambient Junction Storage Temperature Range To determine the junction temperature on the application printed circuit board (PCB), use the following equation: Rating 6.
PAGE 6
ADCLK946 24 23 22 21 20 19 VCC Q0 Q0 Q1 Q1 VEE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADCLK946 TOP VIEW (Not to Scale) 18 17 16 15 14 13 VCC Q2 Q2 Q3 Q3 VCC NOTES: 1. EXPOSED PADDLE MUST BE CONNECTED TO VEE. 08053-002 VEE Q5 Q5 Q4 Q4 VEE 7 8 9 10 11 12 VEE CLK CLK VREF VT VEE Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 7
ADCLK946 TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, VEE = 0.0 V, VICM = VREF, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted. C4 C3 C4 C3 C4 500ps/DIV 100mV/DIV Figure 3. LVPECL Output Waveform @ 200 MHz 08053-006 C3 08053-003 100mV/DIV 100ps/DIV Figure 6. LVPECL Output Waveform @ 1000 MHz 1.8 189 1.6 188 1.5 PROPAGATION DELAY (ps) DIFFERENTIAL OUTPUT VOLTAGE (V) 1.7 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.
PAGE 8
ADCLK946 –90 –100 1.54 1.52 +25°C 1.50 +85°C 1.48 1.46 –110 –120 –130 –150 1.44 –160 1.42 2.75 –170 10 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75 Figure 9. Differential Output Swing vs. Power Supply Voltage vs. Temperature, VID = 1.6 V p-p CLOCK SOURCE 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 11. Absolute Phase Noise Measured @1 GHz with Agilent E5052 300 300 IVCC 250 RANDOM JITTER (fS rms) 250 200 +85°C +25°C –40°C 150 100 IVEE 200 150 100 50 0 2.
PAGE 9
ADCLK946 FUNCTIONAL DESCRIPTION The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs (see Figure 1). Maintain the differential input voltage swing from approximately 400 mV p-p to no more than 3.4 V p-p.
PAGE 10
ADCLK946 PCB LAYOUT CONSIDERATIONS The ADCLK946 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application.
PAGE 11
ADCLK946 INPUT TERMINATION OPTIONS VCC VREF VREF VT VT 50Ω CLK 50Ω CLK 50Ω CLK 50Ω CONNECT VT TO VCC. CONNECT VT TO VREF . Figure 19. Interfacing to CML Inputs 08053-021 08053-019 CLK Figure 21. AC-Coupling Differential Signals Inputs, Such as LVDS VREF VT 50Ω CLK VREF VT 50Ω CLK VCC – 2V 50Ω CLK 50Ω 08053-020 CONNECT VT TO VCC − 2V. CONNECT VT, VREF , AND CLK. PLACE A BYPASS CAPACITOR FROM VT TO GROUND.
PAGE 12
ADCLK946 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ TOP VIEW 0.50 BSC 3.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP SEATING PLANE 19 18 *2.45 EXPOSED PAD 2.30 SQ 2.15 (BOTTOMVIEW) 13 12 7 6 0.23 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 PIN 1 INDICATOR 24 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.