Datasheet

AD9979
Rev. C | Page 22 of 56
HBLK, PBLK, and CLPOB Toggle Positions
The AD9979 uses an internal horizontal pixel counter to position
the HBLK, PBLK, and CLPOB toggle positions. The horizontal
counter does not reset to 0 until 12 CLI periods after the falling
edge of HD. This 12-cycle pipeline delay must be considered
when determining the register toggle positions. For example, if
CLPOBx_TOGy is 100 and the pipeline delay is not considered,
the final toggle position is applied at 112. To obtain the correct
toggle positions, the toggle position registers must be set to the
desired toggle position minus 12. For example, if the desired
toggle position is 100, CLPOBx_TOGy needs to be set to 88,
that is, 100 minus 12. Figure 53 shows the 12-cycle pipeline delay
referenced to the falling edge of HD.
Note that toggle positions cannot be programmed during the
12-cycle delay from the HD falling edge until the horizontal
counter has reset. See Figure 31 for an example of this restriction.
1
HBLKTOGE1/HBLKTOGO1 60 (60 – 12) = 48
2
HBLKTOGE2/HBLKTOGO2 100 (100 – 12) = 88
3
CLPOBx_TOG1 103 (103 – 12) = 91
4
CLPOBx_TOG2 112 (112 – 12) = 100
DESIRED
TOGGLE
POSITION
ACTUAL
REGISTER
VALUE
H1
CLPOB
PIXEL NO.
HD
112103100600
12
34
05957-032
Figure 30. Example of Register Setting to Obtain Desired Toggle Positions
VD
HD
NO TOGGLE POSITIONSALLOWED IN THISAREA
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 12 PIXELS OF PIXEL 0 LOCATION.
H-COUNTER
(PIXEL COUNTER)
N-1 N 0 1 2N-2N-3N-4N-5N-6N-7N-8N-9N-10N-11N-12
H-COUNTER
RESET
XXXX
05957-033
Figure 31. Restriction for Toggle Position Placement