Datasheet

AD9957 Data Sheet
Rev. C | Page 14 of 64
–50
–55
–60
–65
–75
–70
06384-058
SFDR (dBc)
FREQUENCY OUT (MHz)
SFDR WITHOUT PLL
SFDR WITH PLL
0 50 100 150 200 250 300 350 400
Figure 17. Wideband SFDR vs. Output Frequency in Single Tone Mode,
PLL with REFCLK = 15.625 MHz × 64
400 450300250 350200150100500
06384-059
SFDR (dBc)
FREQUENCY OUT (MHz)
–75
–70
–65
–60
–55
–45
–50
LOW SUPPLY
HIGH SUPPLY
Figure 18. SFDR vs. Output Frequency and Supply (±5%) in Single Tone
Mode, REFCLK = 1 GHz
400 450300250 350200150100500
06384-060
SFDR (dBc)
FREQUENCY OUT (MHz)
–75
–70
–65
–60
–55
–50
–40°C
+85°C
Figure 19. SFDR vs. Frequency and Temperature in Single Tone Mode,
REFCLK = 1 GHz
–90
–100
–120
–110
–140
–150
–130
–170
–160
10 100 1k
10k 100k 100M1M 10M
06384-061
MAGNITUDE (dBc/Hz)
FREQUENCY OFFSET (Hz)
f
OUT
= 20.1MHz
f
OUT
= 98.6MHz
f
OUT
= 201.1MHz
f
OUT
= 397.8MHz
Figure 20. Residual Phase Noise, System Clock = 1 GHz
–90
–100
–110
–120
–130
–140
–150
–160
10 100 1k 10k 100k 1M 10M 100M
06384-054
MAGNITUDE (dBc/ Hz)
FREQUENCY OFFSET (Hz)
f
OUT
= 20.1MHz
f
OUT
= 397.8MHz
f
OUT
= 98.6MHz
f
OUT
= 201.1MHz
Figure 21. Residual Phase Noise Using the REFCLK Multiplier,
REFCLK = 50 MHz with 20x Multiplication, System Clock = 1 GHz
1200
200
400
600
800
1000
0
100 200 300 400 500 600 700 800 900 1000
06384-062
POWER DISSIPATION (mW)
SYSTEM CLOCK FREQUENCY (MHz)
DVDD 3.3V
AVDD 3.3V
AVDD 1.8V
DVDD 1.8V
Figure 22. Power Dissipation vs. System Clock (PLL Disabled)