Datasheet

AD9833 Data Sheet
Rev. G | Page 4 of 21
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
1
Table 2.
Parameter Limit at T
MIN
to T
MAX
Unit Description
t
1
40 ns min MCLK period
t
2
16 ns min MCLK high duration
t
3
16 ns min MCLK low duration
t
4
25 ns min SCLK period
t
5
10 ns min SCLK high duration
t
6
10 ns min SCLK low duration
t
7
5 ns min FSYNC to SCLK falling edge setup time
t
8 min
10 ns min FSYNC to SCLK hold time
t
8 max
t
4
− 5 ns max
t
9
5 ns min Data setup time
t
10
3 ns min Data hold time
t
11
5 ns min SCLK high to FSYNC falling edge setup time
1
Guaranteed by design, not production tested.
Timing Diagrams
t
2
t
1
MCLK
t
3
02704-003
Figure 3. Master Clock
t
5
t
4
t
6
t
7
t
8
t
10
t
9
41D51DD0D1D2D14
SCLK
FSYNC
SDATA
D15
t
11
02704-004
Figure 4. Serial Timing