Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 13 of 72
Pin No. Mnemonic Description
K13, K14 DB<11>−/DB<11>+
Negative/Positive Data Input Bit 11 (MSB). Conforms to IEEE-1596
reduced range link.
L1 PIN_MODE 0 = SPI Mode. SPI is enabled.
1 = PIN Mode. SPI disabled; direct pin control.
L7, L8, M7, M8, N7, N8, P7, P8 DVDD33 3.3 V Digital Supply.
L13, L14 DB<10>−/DB<10>+
Negative/Positive Data Input Bit 10. Conforms to IEEE-1596 reduced
range link.
M1, M2 NC No Connect.
M13, M14 DB<9>−/DB<9>+
Negative/Positive Data Input Bit 9. Conforms to IEEE-1596 reduced
range link.
N1, P1 NC No Connect.
N2, P2 DB<0>−/DB<0>+
Negative/Positive Data Input Bit 0 (LSB). Conforms to IEEE-1596
reduced range link.
N3, P3 DB<1>−/DB<1>+
Negative/Positive Data Input Bit 1. Conforms to IEEE-1596 reduced
range link.
N4, P4 DB<2>−/DB<2>+
Negative/Positive Data Input Bit 2. Conforms to IEEE-1596 reduced
range link.
N5, P5 DB<3>−/DB<3>+
Negative/Positive Data Input Bit 3. Conforms to IEEE-1596 reduced
range link.
N6, P6 DATACLK_OUT−/
DATACLK_OUT+
Negative/Positive Data Output Clock. Conforms to IEEE-1596
reduced range link.
N9, P9 DATACLK_IN−/
DATACLK_IN+
Negative/Positive Data Input Clock. Conforms to IEEE-1596 reduced
range link.
N10, P10 DB<4>−/DB<4>+
Negative/Positive Data Input Bit 4. Conforms to IEEE-1596 reduced
range link.
N11, P11 DB<5>−/DB<5>+
Negative/Positive Data Input Bit 5. Conforms to IEEE-1596 reduced
range link.
N12, P12 DB<6>−/DB<6>+
Negative/Positive Data Input Bit 6. Conforms to IEEE-1596 reduced
range link.
N13, P13 DB<7>−/DB<7>+
Negative/Positive Data Input Bit 7. Conforms to IEEE-1596 reduced
range link.
N14, P14 DB<8>−/DB<8>+
Negative/Positive Data Input Bit 8. Conforms to IEEE-1596 reduced
range link.