Datasheet

AD9520-5 Data Sheet
Rev. A | Page 8 of 76
Parameter Min Typ Max Unit Test Conditions/Comments
Source Current Damage to the part can result if values are exceeded
Static 20 mA
Dynamic 16 mA
Sink Current Damage to the part can result if values are exceeded
Static 8 mA
Dynamic 16 mA
TIMING CHARACTERISTICS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT RISE/FALL TIMES Termination = 50 Ω to V
S_DRV
− 2 V
Output Rise Time, t
RP
130 170 ps 20% to 80%, measured differentially (rise/fall times are
independent of V
S
and are valid for V
S_DRV
= 3.3 V and 2.5 V)
Output Fall Time, t
FP
130 170 ps 80% to 20%, measured differentially (rise/fall times are
independent of V
S
and are valid for V
S_DRV
= 3.3 V and 2.5 V)
PROPAGATION DELAY, t
PECL
, CLK-TO-LVPECL
OUTPUT
For All Divide Values 850 1050 1280 ps High frequency clock distribution configuration
800 970 1180 ps Clock distribution configuration
Variation with Temperature 1.0 ps/°C
OUTPUT SKEW, LVPECL OUTPUTS
1
Termination = 50 Ω to V
S_DRV
− 2 V
LVPECL Outputs Sharing the Same Divider 5 16 ps V
S_DRV
= 3.3 V
5 20 ps V
S_DRV
= 2.5 V
LVPECL Outputs on Different Dividers 5 45 ps V
S_DRV
= 3.3 V
5
60
ps
V
S_DRV
= 2.5 V
All LVPECL Outputs Across Multiple Parts 190 ps V
S_DRV
= 3.3 V and 2.5 V
CMOS OUTPUT RISE/FALL TIMES Termination = open
Output Rise Time, t
RC
750
960
ps
20% to 80%; C
LOAD
= 10 pF; V
S_DRV
= 3.3 V
Output Fall Time, t
FC
715
890
ps
80% to 20%; C
LOAD
= 10 pF; V
S_DRV
= 3.3 V
Output Rise Time, t
RC
965 1280 ps 20% to 80%; C
LOAD
= 10 pF; V
S_DRV
= 2.5 V
Output Fall Time, t
FC
890 1100 ps 80% to 20%; C
LOAD
= 10 pF; V
S_DRV
= 2.5 V
PROPAGATION DELAY, t
CMOS
, CLK-TO-CMOS
OUTPUT
Clock distribution configuration
For All Divide Values 2.1 2.75 3.55 ns V
S_DRV
= 3.3 V
3.35 ns V
S_DRV
= 2.5 V
Variation with Temperature 2 ps/°C V
S_DRV
= 3.3 V and 2.5 V
OUTPUT SKEW, CMOS OUTPUTS
1
CMOS Outputs Sharing the Same Divider 7 85 ps V
S_DRV
= 3.3 V
10 105 ps V
S_DRV
= 2.5 V
All CMOS Outputs on Different Dividers 10 240 ps V
S_DRV
= 3.3 V
10 285 ps V
S_DRV
= 2.5 V
All CMOS Outputs Across Multiple Parts 600 ps V
S_DRV
= 3.3 V
620 ps V
S_DRV
= 2.5 V
OUTPUT SKEW, LVPECL-TO-CMOS OUTPUTS
1
All settings identical; different logic type
Outputs Sharing the Same Divider 1.18 1.76 2.48 ns LVPECL to CMOS on same part
Outputs on Different Dividers 1.20 1.78 2.50 ns LVPECL to CMOS on same part
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.