Datasheet

AD9520-5 Data Sheet
Rev. A | Page 30 of 76
Phase-Locked Loop (PLL)
Figure 29. PLL Functional Block Diagram
The AD9520 includes on-chip PLL blocks that can be used with
an external VCO or VCXO to create a complete phase-locked
loop. The PLL requires an external loop filter, which usually
consists of a small number of capacitors and resistors. The
configuration and components of the loop filter help to
establish the loop bandwidth and stability of the PLL.
The AD9520 PLL is useful for generating clock frequencies
from a supplied reference frequency. This includes conversion
of reference frequencies to much higher frequencies for subsequent
division and distribution. In addition, the PLL can be used to
clean up jitter and phase noise on a noisy reference. The exact
choice of PLL parameters and loop dynamics is application specific.
The flexibility and depth of the AD9520 PLL allow the part to
be tailored to function in many different applications and signal
environments.
Configuration of the PLL
Configuration of the PLL is accomplished by programming
the various settings for the R divider, N divider, PFD polarity,
and charge pump current. The combination of these settings
determines the PLL loop bandwidth. These are managed through
programmable register settings (see Table 44 and Table 48) and
by the design of the external loop filter.
Successful PLL operation and satisfactory PLL loop performance
are highly dependent upon proper configuration of the PLL
settings, and the design of the external loop filter is crucial to
the proper operation of the PLL.
ADIsimCLK™ is a free program that can help with the design
and exploration of the capabilities and features of the AD9520,
including the design of the PLL loop filter.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and the N divider and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by Register 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD. The maximum input frequency into the
PFD is a function of the antibacklash pulse setting, as specified
in the phase/frequency detector (PFD) parameter in Table 2.
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the external VCO to move the VCO frequency
up or down. The CP can be set (Register 0x010[3:2]) for high
impedance (allows holdover operation), for normal operation
(attempts to lock the PLL loop), or for pump up or pump down
(test modes). The CP current is programmable in eight steps from
(nominally) 0.6 mA to 4.8 mA. The CP current LSB is set by the
CP
RSET
resistor, which is nominally 5.1 kΩ. The exact value of
the CP current can be calculated with the following equation:
I
CP
(A) =
)(
06.3

RSET
CP
PROGRAMMABLE
N DELAY
CLK
CLK
R
DIVIDER
CLOCK
DOUBLER
STATUS
PROGRAMMABLE
R DELAY
CPRSET
V
CP
V
S GND RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PLL
REFERENCE
HOLD
01
DIVIDE BY 1,
2, 3, 4, 5, OR 6
ZERO DELAY BLOCK
FROM CHANNEL
DIVIDER 0
VS_DRV
07239-064
REFIN
REF1
REF2
BUF
AMP
REFERENCE
SWITCHOVER
REF_SEL
REFIN
STATUS
STATUS
OPTIONAL