Datasheet

AD9520-5 Data Sheet
Rev. A | Page 20 of 76
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off),
LVPECL Outputs Terminated 50 Ω to V
S_DRV
− 2 V
Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off),
CMOS Outputs with 10 pF Load
Figure 8. Charge Pump Characteristics at CP
V
= 3.3 V
Figure 9. Charge Pump Characteristics at CP
V
= 5.0 V
Figure 10. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
Figure 11. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/
REFIN
350
300
250
200
150
100
0 500 1000 1500 2000 2500 3000
CURRENT (mA)
FREQUENCY (MHz)
3 CHANNELS—6 LVPECL
3 CHANNELS—3 LVPECL
2 CHANNELS—2 LVPECL
1 CHANNEL—1 LVPECL
07239-108
240
220
200
180
160
140
120
100
80
0 50 100 150 200 250
CURRENT (mA)
FREQUENCY (MHz)
3 CHANNELS—6 CMOS
3 CHANNELS—3 CMOS
2 CHANNELS—2 CMOS
1 CHANNEL—1 CMOS
07239-109
5
4
3
2
1
0
0 3.53.02.52.01.51.00.5
CURRENT FROM CP PIN (mA)
VOLTAGE ON CP PIN (V)
PUMP UPPUMP DOWN
07239-111
5
4
3
2
1
0
0 5.04.03.0 4.53.52.52.01.51.00.5
CURRENT FROM CP PIN (mA)
VOLTAGE ON CP PIN (V)
PUMP DOWN PUMP UP
07239-112
–140
–145
–150
–155
–160
–165
–170
0.1 1 10010
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
PFD FREQUENCY (MHz)
07239-013
–208
–210
–212
–214
–216
–218
–220
–222
–224
0 0.4 0.8 1.20.2 0.6 1.0 1.4
PLL FIGURE OF MERIT (dBc/Hz)
INPUT SLEW RATE (V/ns)
DIFFERENTIAL INPUT
SINGLE-ENDED INPUT
07239-114