Datasheet

AD9520-5 Data Sheet
Rev. A | Page 12 of 76
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 9.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz;
Channel Divider = 2; Duty-Cycle Correction = Off
230 fs rms Calculated from SNR of ADC method
(broadband jitter)
CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = On
215 fs rms Calculated from SNR of ADC method
(broadband jitter)
CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
326 fs rms Calculated from SNR of ADC method
(broadband jitter)
CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz;
Channel Divider = 8; Duty-Cycle Correction = Off
362 fs rms Calculated from SNR of ADC method
(broadband jitter)
SERIAL CONTROL PORT—SPI MODE
Table 10.
Parameter Min Typ Max Unit Test Conditions/Comments
CS
(INPUT)
CS
has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 3 µA
Input Logic 0 Current −110 µA The minus sign indicates that current is
flowing out of the AD9520, which is due to
the internal pull-up resistor
Input Capacitance 2 pF
SCLK (INPUT) IN SPI MODE SCLK has an internal 30 kΩ pull-down resistor
in SPI mode, but not in I
2
C mode
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current
110
µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO (INPUT IN BIDIRECTIONAL MODE)
Input Logic 1 Voltage 2.0 V
Input Logic 0 Voltage 0.8 V
Input Logic 1 Current 1 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage 2.7 V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/t
SCLK
) 25 MHz
Pulse Width High, t
HIGH
16
ns
Pulse Width Low, t
LOW
16 ns
SDIO to SCLK Setup, t
DS
4 ns
SCLK to SDIO Hold, t
DH
0 ns
SCLK to Valid SDIO and SDO, t
DV
11 ns
CS
to SCLK Setup and Hold, t
S
, t
C
2 ns
CS
Minimum Pulse Width High, t
PWH
3
ns