Datasheet

AD8335 Data Sheet
Rev. B | Page 18 of 28
Figure 56 shows the simulated noise figure (NF) vs. source
resistance, and various values of preamplifier R
IN
from 50 Ω to
14.7 kΩ, the value seen looking into the PIPx pins when R
FB
= ∞.
As shown in the figure, the minimum NF for R
IN
= 50 Ω is slightly
less than 7 dB. Note that, for this preamplifier, the NF is optimized
for the R
IN
from 50 Ω to 200 Ω; for R
FB
= ∞, the minimum NF is at
approximately 480 Ω. This optimum noise resistance can also be
calculated by dividing the input referred voltage noise by the
current noise.
0
2
4
6
8
10
NOISE FIGURE (dB)
12
14
16
R
S
()
10 100 1k
04976-066
R
IN
= 50
R
FB
= 250
R
IN
= 75
R
FB
= 375
R
IN
= 100
R
FB
= 500
R
IN
= 200
R
FB
= 1k
R
IN
= 14.7k
R
FB
=
SIMULATION
INCLUDES NOISE OF VGA
f = 1MHz
Figure 56. Simulated Noise Figure vs. R
S
for
Various Fixed Values of R
IN
, Actively Matched
VGA
As seen in Figure 54, the basic architecture, an X-AMP®, consists of
a ladder attenuator, followed by a fixed gain amplifier with selectable
input stages. Earlier examples of this architecture are to be found in
the AD60x series, AD8331/AD8332, andAD8367 VGAs. Through
a proprietary, temperature-compensated interpolator design, the
bias currents to the input g
m
stages are continuously steered from
right to left (decreasing attenuation) resulting in increasing gain.
The HLxx gain pins (HL12 and HL34) select one of two output
amplifier networks consisting of the feedback resistors, amplifier
stages, and buffers.
Optimizing the System Dynamic Range
The VGA output gain switch of 8 dB (×2.5) optimizes the VGA
noise floor for a 10-bit or 12-bit ADC, assuming a full-scale ADC
input voltage of 1 V p-p.
At low gain, the ADC SNR should limit the system noise
performance, whereas at high gains, the noise is defined by
the source and preamplifier. The maximum voltage swing is
bounded by the full-scale, peak-to-peak ADC input voltage
(typically 1 V p-p to 2 V p-p). The noise performance is optimized
by adjusting the noise floor of the VGA according to the ADC
resolution. The SNR of a 12-bit converter is theoretically 12 dB
better than a 10-bit; however, approximately 8 dB is typical in
practice, accounting for the 8 dB gain option of the AD8335. The
IRN and the power consumption of the VGA are unaffected by
either gain setting; therefore, only the output referred noise
(ORN) changes (by 8 dB) without affecting any other parameters.
Attenuator
The attenuator is an 8-stage differential R-2R ladder with a total
attenuation of 48.16 dB or 6.02 dB per tap. The effective input
resistance per side is 320 Ω nominal for a total differential resis-
tance of 640 Ω. The common-mode voltage of the attenuator
and the VGA is controlled by an amplifier that uses the same
midsupply voltage derived in the preamplifier, permitting dc
coupling of the PrA to the VGA without introducing large offsets
due to common-mode differences. However, when dc coupling
between the PrA and VGA, any offset from the PrA is amplified
as the gain is increased, producing an exponentially increasing
VGA output offset. When the PrA and the VGA are ac-coupled,
the output offset is unchanged with changes in gain (see Figure 15).
As a result, ac coupling is recommended for most applications.
As can be seen from Figure 54, The VCMx pins connect to the
respective midpoints on each channel and are used to ac decouple
the common-mode node at high frequencies. It is very important
that at least a 0.1 µF capacitor be used, with better decoupling at
higher frequencies when another smaller capacitor (10 nF) is
connected in parallel. The internal +1 buffer provides correct
common-mode bias levels and any dynamic currents have to be
absorbed by the external decoupling capacitors.
Gain Control
The gain control interface has two inputs, V
GAIN
(VGNx pins)
and VSLP (SLxx pins). The slope input is intended only as a
decoupling pin, and the only guaranteed gain slope is the
20 dB/V default. However, if a voltage is applied to the VSLP
inputs, the gain slope can be increased by reducing the slope
voltage. For example, if a voltage of 1.67 V is applied to the SLxx
pins, the gain slope changes to 30 dB/V. Use Equation 4 to
calculate the gain slope.
Slope
VSLP
dB/V1.20V5.2 ×
=
(4)
V
GAIN
varies the gain of the VGA through the interpolator by
selecting the appropriate input stages connected to the input
attenuator. The nominal V
GAIN
range for 20 dB/V is 0 V to 3 V,
with the best gain linearity from approximately 0.5 V to 2.5 V,
where the error is typically less than ±0.2 dB. For V
GAIN
voltages
above 2.5 V and less than 0.5 V, the error increases (see Figure 4).
The value of the V
GAIN
voltage can be increased to that of the
supply voltage, without gain foldover.
Each channel has separate gain control pins that can be connected
to a common voltage source such as found in most ultrasound
applications. For control of individual channels, connect the
appropriate gain control signal to each channel.