Datasheet

AD8275
Rev. A | Page 11 of 16
THEORY OF OPERATION
The AD8275 level translates ±10 V signals at its inputs to 4 V
at its output. It does this by attenuating the input signal by 5.
A subtractor network performs the attenuation, the level shifting,
and the differential-to-single-ended conversion. One benefit of
the subtractor topology is that it can accept input signals
beyond its supply voltage. The subtractor is composed of tightly
matched resistors. By integrating the resistors and trimming the
resistor ratios, the AD8275 achieves 80 dB CMRR and 0.024%
gain error.
07546-030
INPUT
ESD
REF2
+V
S
+V
S
+V
S
–V
S
–V
S
+V
S
–V
S
–V
S
+V
S
–V
S
–V
S
OUT
SENSE
50kΩ
7kΩ
7kΩ
50kΩ
20kΩ
20kΩ
10kΩ
2.5V
–IN
+IN
INPUT
ESD
+V
S
–V
S
REF1
+V
S
–V
S
Figure 31. AD8275 Simplified Schematic
To achieve a wider input voltage range, the AD8275 uses an
internal 2.5 V voltage bias tied to –V
S
and two 7 kΩ resistors, as
shown in Figure 31. The resistors help to set the common mode
of the internal amplifier. The benefit of this circuit is that it
extends the input range without causing crossover distortion
typical of amplifiers that have rail-to-rail complementary
transistor inputs. The input range of the internal op amp is
+V
S
− 0.9 V to −V
S
+ 1.35 V.
–10 –8 –6
600
400
200
0
–200
–400
–600
–4 –2 0 2 4 6 8 10
COMMON-MODE VOLTAGE (V)
OFFSET (µV)
07546-132
Figure 32. AD8275 Does Not Have Crossover Distortion Typical of Rail-to-Rail
Input Amplifiers
The AD8275 employs a balanced, high gain, linear output stage
that adaptively generates current as required, eliminating the
dynamic errors found in other amplifiers. This is useful when
driving SAR ADCs, which can deliver kickback current into the
output of the amplifier. The result is a design that achieves low
distortion, consistent bandwidth, and high slew rate.
BASIC CONNECTION
The basic configurations for the AD8275 are shown in
Figure 33 and Figure 34. In Figure 33, REF1 and REF2 are
tied together. A voltage, V
REF
, applied to the tied REF1 and
REF2 pins, sets the output voltage level to V
REF
. For example,
in Figure 33, if V
REF
= 2 V and the inputs are tied to ground,
the output remains at 2 V.
07546-031
AD8275
7
4
5
6
8
1
2
50kΩ
0.1µF
50kΩ
20kΩ
20kΩ
10kΩ
3
V
INN
+IN
–IN
V
INP
REF2
V
REF
V
OUT
REF1
–V
S
+V
S
+5V
OUT
SENSE
V
OUT
= + V
REF
(V
INP
) – (V
INN
)
5
Figure 33. Basic Configuration 1: Shared Reference
In contrast, Figure 34 shows REF1 tied to ground and REF2
tied to V
REF
. In this example, the two 20 kΩ resistors serve as a
resistor divider, and V
REF
is divided by 2. For example, if both
inputs of the AD8275 are grounded and V
REF
= 5 V, the output
is 2.5 V.
07546-032
AD8275
7
4
5
6
8
1
2
50kΩ
0.1µF
50kΩ
20kΩ
20kΩ
10kΩ
3
V
INN
+IN
–IN
V
INP
REF2
V
REF
V
OUT
REF1
–V
S
+V
S
+5V
OUT
SENSE
V
OUT
= +
(V
INP
) – (V
INN
)
5
V
REF
+ 0V
2
Figure 34. Basic Configuration 2: Split Reference