Datasheet

AD8132
Rev. I | Page 24 of 32
When using the AD8132 in gain configurations where β1 ≠ β2,
differential output noise appears due to input-referred voltage
noise in the V
OCM
circuitry according to the following formula:
In cases where more accurate control of the output common-mode
level is required, it is a best practice that an external source or
resistor divider (with R
SOURCE
< 10 kΩ) be used. The output
common-mode offset values in the Specifications section assume
the V
OCM
input is driven by a low impedance voltage source.
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
+
−
=
β2β1
β2β1
VV
NOCMOND
2
DRIVING A CAPACITIVE LOAD
where:
V
OND
is the output differential noise.
V
NOCM
is the input-referred voltage noise on V
OCM
.
A purely capacitive load can react with the pin and bond wire
inductance of the AD8132, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance must be small to avoid destabilizing the amplifier. An
alternative technique is to place a small resistor in series with
the amplifier outputs, as shown in Figure 60.
CALCULATING INPUT IMPEDANCE OF THE
APPLICATION CIRCUIT
The effective input impedance of a circuit, such as that in Figure 64,
at +D
IN
and −D
IN
, depends on whether the amplifier is being
driven by a single-ended or differential signal source. For balanced
differential input signals, the input impedance (R
IN, dm
) between
the inputs (+D
IN
and −D
IN
) is simply
OPEN-LOOP GAIN AND PHASE
Open-loop gain and phase plots are shown in Figure 65 and
Figure 66.
R
IN, dm
= 2 × R
G
–20
–10
0
10
20
30
40
50
60
0.1 1 10 100 1000
FREQUENCY (MHz)
OPEN-LOOP GAIN (dB)
R
L, dm
= 2kΩ
01035-083
In the case of a single-ended input signal (for example, if −D
IN
is grounded and the input signal is applied to +D
IN
), the input
impedance becomes
()
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
+
×
−
=
F
G
F
G
dmIN,
RR
R
R
R
2
1
The circuit input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor, R
G
.
Figure 65. Open-Loop Gain vs. Frequency
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
20
40
0.1 1 10 100 1000
FREQUENCY (MHz)
OPEN-LOOP PHASE (Degrees)
R
L, dm
= 2kΩ
01035-084
The AD8132 is optimized for level-shifting, ground-referenced
input signals. For a single-ended input, this implies that the voltage
at −D
IN
in Figure 64 is 0 V when the negative power supply
voltage (at V−) of the amplifier is also set to 0 V.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The V
OCM
pin of the AD8132 is internally biased at a voltage
approximately equal to the midsupply point (average value of the
voltage on V+ and V−). Relying on this internal bias results in an
output common-mode voltage that is within approximately
100 mV of the expected value.
Figure 66. Open-Loop Phase vs. Frequency