Datasheet

REV. A–4–
AD7866
TIMING SPECIFICATIONS
1
(V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, V
REF
= 2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Limit at
Parameter T
MIN
, T
MAX
Unit Description
f
SCLK
2
10 kHz min
20 MHz max
t
CONVERT
16  t
SCLK
ns max t
SCLK
= 1/f
SCLK
800 ns max f
SCLK
= 20 MHz
t
QUIET
50 ns max Minimum Time between End of Serial Read and Next Falling Edge of CS
t
2
10 ns min CS to SCLK Setup Time
t
3
3
25 ns max Delay from CS until D
OUT
A and D
OUT
B Three-State Disabled
t
4
3
40 ns max Data Access Time after SCLK Falling Edge. V
DRIVE
 3 V, C
L
= 50 pF;
V
DRIVE
< 3 V, C
L
= 25 pF
t
5
0.4 t
SCLK
ns min SCLK Low Pulsewidth
t
6
0.4 t
SCLK
ns min SCLK High Pulsewidth
t
7
10 ns min SCLK to Data Valid Hold Time
t
8
4
25 ns max CS Rising Edge to D
OUT
A, D
OUT
B, High Impedance
t
9
4
10 ns min SCLK Falling Edge to D
OUT
A, D
OUT
B, High Impedance
50 ns max SCLK Falling Edge to D
OUT
A, D
OUT
B, High Impedance
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the CLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8,
t
9
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t
8
and t
9
quoted in the timing characteristics are the true
bus relinquish times of the part and are independent of the bus loading.
Specifications subject to change without notice.
1.6V
200␮AI
OL
200␮A
I
OH
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing Specifications