User guide

Parameter Value Description
Enable Altera Debug
Master Endpoint
On/Off When you turn on this option, the Transceiver Native PHY IP
includes an embedded Altera Debug Master Endpoint (ADME) that
connects internally to the Avalon-MM slave interface for dynamic
reconfiguration. The ADME can access the reconfiguration space of
the transceiver. It can perform certain test and debug functions via
JTAG using the System Console. This option requires you to enable
the Share reconfiguration interface option for configurations
using more than one channel.
Table 2-33: Optional Reconfiguration Logic
Parameter Value Description
Enable capability
registers
On/Off Enables capability registers that provide high level information about the
configuration of the transceiver channel.
Set user-defined IP
identifier
User-defined Sets a user-defined numeric identifier that can be read from the user_
identifier offset when the capability registers are enabled.
Enable control and
status registers
On/Off Enables soft registers to read status signals and write control signals on the
PHY interface through the embedded debug.
Enable PRBS
(Pseudo Random
Binary Sequence)
soft accumulators
On/Off Enables soft logic for performing PRBS bit and error accumulation when
the hard PRBS generator and checker are used.
Enable On-Die
Instrumentation
(ODI) acceleration
logic
On/Off Enables soft logic for accelerating bit and error accumulation when using
ODI.
Table 2-34: Configuration Files
Parameter Value Description
Configuration file
prefix
<prefix> Here, the file prefix to use for generated configuration files is
specified. Each variant of the Transceiver Native PHY IP should use
a unique prefix for configuration files.
Generate
SystemVerilog
package file
On/Off When you turn on this option, the Transceiver Native PHY IP
generates a SystemVerilog package file, _reconfig_parameters.sv.
This file contains parameters defined with the attribute values
required for reconfiguration.
Generate C header
file
On/Off When you turn on this option, the Transceiver Native PHY IP
generates a C header file, _reconfig_parameters.h. This file
contains macros defined with the attribute values required for
reconfiguration.
UG-01143
2015.05.11
Dynamic Reconfiguration Parameters
2-47
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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