User guide

Parameter Range Description
RX rate match
insert/delete +ve
pattern (hex)
User-specified 20
bit pattern
Specifies the +ve (positive) disparity value for the RX rate
match FIFO as a hexadecimal string.
RX rate match
insert/delete -ve
pattern (hex)
User-specified 20
bit pattern
Specifies the -ve (negative) disparity value for the RX rate
match FIFO as a hexadecimal string.
Enable rx_std_
rmfifo_full port
On / Off Enables the optional rx_std_rmfifo_full port.
Enable rx_std_
rmfifo_empty port
On / Off Enables the rx_std_rmfifo_empty port.
PCI Express Gen3
rate match FIFO
mode
Bypass
0 ppm
600 ppm
Specifies the PPM tolerance for the PCI Express Gen3 rate
match FIFO.
Table 2-28: Word Aligner and Bitslip Parameters
Parameter Range Description
Enable TX bitslip On / Off When you turn on this option, the PCS includes the bitslip
function. The outgoing TX data can be slipped by the
number of bits specified by the tx_std_bitslipboundar-
ysel control signal.
Enable tx_std_bitslip‐
boundarysel port
On / Off Enables the tx_std_bitslipboundarysel control signal.
RX word aligner mode
bitslip
manual (PLD
controlled)
synchronous
state machine
deterministic
latency
Specifies the RX word aligner mode for the Standard PCS.
The word aligned width depends on the PCS and PMA
width, and whether or not 8B/10B is enabled.
RX word aligner pattern
length
7, 8, 10, 16, 20,
32, 40
Specifies the length of the pattern the word aligner uses for
alignment.
(29)
RX word aligner pattern
(hex)
User-specified Specifies the word alignment pattern in hex.
(29)
Refer toTable 2-11 in the Arria 10 Standard PCS Architecture chapter. It shows the possible values of
"Rx Word Aligner Pattern Length" in all available word aligner modes.
2-42
Standard PCS Parameters
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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