User guide

Parameter Range Description
Enable rx_enh_
highber_clr_cnt
port
(10GBASE-R)
On / Off Enables the rx_enh_highber_clr_cnt input port. For the
10GBASE-R transceiver configuration rule, this signal is
asserted to clear the internal counter. This counter indicates the
number of times the BER state machine has entered the "BER_
BAD_SH" state. This is an asynchronous signal.
Enable rx_enh_
clr_errblk_count
port
(10GBASE-R)
On / Off Enables the rx_enh_clr_errblk_count input port. For the
10GBASE-R transceiver configuration rule, this signal is
asserted to clear the internal counter. This counter indicates the
number of the times the RX state machine has entered the RX_
E state. For protocols with FEC block enabled, this signal is
asserted to reset the status counters within the RX FEC block.
This is an asynchronous signal.
Table 2-17: 64b/66b Encoder and Decoder Parameters
Parameter Range Description
Enable TX 64b/
66b encoder
On / Off When you turn on this option, the Enhanced PCS enables the
TX 64b/66b encoder.
Enable RX 64b/
66b decoder
On / Off When you turn on this option, the Enhanced PCS enables the
RX 64b/66b decoder.
Enable TX sync
header error
insertion
On / Off When you turn on this option, the Enhanced PCS supports
cycle-accurate error creation to assist in exercising error
condition testing on the receiver. When error insertion is
enabled and the error flag is set, the encoding sync header for
the current word is generated incorrectly. If the correct sync
header is 2'b01 (control type), 2'b00 is encoded. If the correct
sync header is 2'b10 (data type), 2'b11 is encoded.
Table 2-18: Scrambler and Descrambler Parameters
Parameter Range Description
Enable TX
scrambler
(10GBASE-R/
Interlaken)
On / Off Enables the scrambler function. This option is available for the
Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R
protocols. You can enable the scrambler in Basic (Enhanced
PCS) mode when the block synchronizer is enabled and with
66:32, 66:40, or 66:64 gear box ratios.
TX scrambler
seed (10GBASE-
R/Interlaken)
User-specified 58-bit
value
You must provide a non-zero seed for the Interlaken protocol.
For a multi-lane Interlaken Transceiver Native PHY IP, the first
lane scrambler has this seed. For other lanes' scrambler, this
seed is increased by 1 per each lane. The initial seed for
10GBASE-R is 0x03FFFFFFFFFFFFFF. This parameter is
required for the 10GBASE-R and Interlaken protocols.
2-36
Enhanced PCS Parameters
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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