User guide

Parameters Value Description
Number of fixed DFE taps 3 , 7 Specifies the number of fixed DFE taps. Select the
number of taps depending on the loss in your
transmission channel and the type of equalization
required.
Table 2-9: RX PMA Optional Ports
Parameters Value Description
Enable rx_pma_
clkout port
On/Off Enables the optional rx_pma_clkout output clock. This port is
the recovered parallel clock from the RX clock data recovery
(CDR).
(28)
Enable rx_pma_
div_clkout port
On/Off Enables the optional rx_pma_div_clkout output clock. The
deserializer generates this clock. Use this to drive core logic, to
drive the RX PCS-to-FPGA fabric interface, or both.
If you specify a rx_pma_div_clkout division factor of 1 or 2,
this clock output is derived from the PMA parallel clock. If you
specify a rx_pma_div_clkout division factor of 33, 40, or 66,
this clock is derived from the PMA serial clock. This clock is
commonly used when the interface to the RX FIFO runs at a
different rate than the PMA parallel clock frequency, such as
66:40 applications.
Enable rx_pma_
div_clkout
division factor
port
Disabled, 1, 2, 33,
40, 66
Specifies the division factor for the rx_pma_div_clkout output
clock when this port is enabled.
Enable rx_pma_
iqtxrx_clkout
port
On/Off Enables the optional rx_pma_iqtxrx_clkout output clock.
This clock can be used to cascade the RX PMA output clock to
the input of a PLL.
Enable rx_pma_
clkslip port
On/Off Enables the optional rx_pma_clkslip control input port. A
rising edge on this signal causes the RX serializer to slip the
serial data by one clock cycle, or 2 unit intervals (UI).
Enable rx_pma_
qpipulldn port
(QPI)
On/Off Enables the rx_pma_qpipulldn control input port. Use this
port only for QPI applications.
Enable rx_is_
lockedtodata
port
On/Off Enables the optional rx_is_lockedtodata status output port.
This signal indicates that the RX CDR is currently in lock to
data mode or is attempting to lock to the incoming data stream.
This is an asynchronous output signal.
(28)
This clock should not be used to clock the FPGA - transceiver interface. This clock may be used as a
reference clock to an external clock cleaner.
2-28
PMA Parameters
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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