User guide

Figure 6-10: Timing Diagram for Embedded Streamer Reconfiguration
reconfig_clk
reconfig_address
reconfig_read
reconfig_readdata
reconfig_waitrequest
reconfig_write
reconfig_writedata
xxx 0x340h 0x341h 0x000h
0x00h0x01h0x01h0x01h0x00hxxx
0x00h 0x00h0x81h 0x00h
User Requests
Streaming
User Polls
Streaming
Busy Bit
Streaming in
Progress; Streaming
Busy Bit Is High
Streaming Completes;
Streaming Busy Bit Is Low
Reconfiguration Flow for Special Cases
Dynamic reconfiguration can be performed on logical operations such as switching between multiple
transmit PLLs or multiple reference clocks. In these cases, configuration files alone cannot be used.
Configuration files are generated during IP generation and do not contain information on the placement
of PLLs or reference clocks.
To perform dynamic reconfiguration on logical operations, you must use lookup registers that contain
information about logical index to physical index mapping. Lookup registers are read-only registers. Use
these lookup registers to perform a read-modify-write to the selection MUXes to switch between PLLs or
reference clocks.
Switching Transmitter PLL
Dynamically switching data rates increases system flexibility to support multiple protocols. You can
change the transceiver channel data rate by switching from one transmit PLL to another. To switch
between transmit PLLs, you must reconfigure the local CGB MUX select lines of the channel by
performing a channel reconfiguration. You can clock transceiver channels with up to four different
transmitter PLLs. You can use the reconfiguration interface on the Native PHY IP to specify which PLL
drives the transceiver channel. The PLL switching method is the same, regardless of the number of
transmitter PLLs involved.
Before initiating the PLL switch procedure, ensure that your Transceiver Native PHY instance defines
more than one transmitter PLL input. Specify the Number of TX PLL clock inputs per channel
parameter on the TX PMA tab during Transceiver Native PHY parameterization.
The following table shows the addresses and bits for transmitter PLL switching. The number of exposed
tx_serial_clk bits varies according to the number of transmitter PLLs you specify. Use the Native PHY
reconfiguration interface for this operation.
UG-01143
2015.05.11
Reconfiguration Flow for Special Cases
6-19
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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