User guide

signal is asserted active high to indicate that the CDR has locked to the phase and frequency of the
receiver input reference clock.
Note: The phase detector (PD) is inactive in LTR mode.
Lock-to-Data Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial
data. In LTD mode, the PD in the CDR tracks the incoming serial data at the receiver input. Depending
on the phase difference between the incoming data and the CDR output clock, the PD controls the CDR
charge pump that tunes the VCO.
Note: The PFD is inactive in LTD mode. The rx_is_lockedtoref status signal toggles randomly and is
not significant in LTD mode.
After switching to LTD mode, the rx_is_lockedtodata status signal is asserted. The actual lock time
depends on the transition density of the incoming data and the parts per million (ppm) difference
between the receiver input reference clock and the upstream transmitter reference clock. The
rx_is_lockedtodata signal toggles until the CDR sees valid data; therefore, you should hold receiver
PCS logic in reset (rx_digitalreset) for a minimum of 4 µs after rx_is_lockedtodata remains
continuously asserted.
CDR Lock Modes
You can configure the CDR in either automatic lock mode or manual lock mode. By default, the Quartus
II software configures the CDR in automatic lock mode.
Automatic Lock Mode
In automatic lock mode, the CDR initially locks to the input reference clock (LTR mode). After the CDR
locks to the input reference clock, the CDR locks to the incoming serial data (LTD mode) when the
following conditions are met:
• The signal threshold detection circuitry indicates the presence of valid signal levels at the receiver
input buffer when rx_std_signaldetect is enabled.
• The CDR output clock is within the configured ppm frequency threshold setting with respect to the
input reference clock (frequency locked).
• The CDR output clock and the input reference clock are phase matched within approximately
0.08 unit interval (UI) (phase locked).
If the CDR does not stay locked to data because of frequency drift or severe amplitude attenuation, the
CDR switches back to LTR mode.
Manual Lock Mode
The PPM detector and phase relationship detector reaction times can be too long for some applications
that require faster CDR lock time. You can manually control the CDR to reduce its lock time using two
optional input ports (rx_set_locktoref and rx_set_locktodata).
Table 5-3: Relationship Between Optional Input Ports and the CDR Lock Mode
rx_set_locktoref rx_set_locktodata CDR Lock Mode
0 0 Automatic
UG-01143
2015.05.11
Lock-to-Data Mode
5-15
Arria 10 Transceiver PHY Architecture
Altera Corporation
Send Feedback