User guide

Figure 4-8: Altera Transceiver PHY Reset Controller System Diagram
Transceiver
PHY Reset
Controller
IP Core
Transceiver PHY Instance
Receiver
PCS
Transmitter
PCS
Transmitter
PMA
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
tx_cal_busy
rx_cal_busy
rx_is_lockedtodata
Transmit
PLL
pll_powerdown
pll_locked
clock
Receiver
PMA
CDR
pll_tx_cal_busy
pll_cal_busy
reset
tx_ready rx_ready
Status Signals
You can logical OR the pll_cal_busy
and tx_cal_busy signals.
pll_tx_cal_busy connects to the
controller’s tx_cal_busy input port.
The Transceiver PHY Reset Controller IP core connects to the Transceiver PHY and the Transmit PLL.
The Transceiver PHY Reset Controller IP core receives status from the Transceiver PHY and the
Transmit PLL. Based on the status signals or the reset input, it generates TX and RX reset signals to the
Transceiver PHY and TX PLL.
The tx_ready signal indicates whether the TX PMA exits the reset state, and if the TX PCS is ready to
transmit data. The rx_ready signal indicates whether the RX PMA exits the reset state, and if the RX PCS
is ready to receive data. You must monitor these signals to determine when the transmitter and receiver
are out of the reset sequence.
4-10
Using the Altera Transceiver PHY Reset Controller
UG-01143
2015.05.11
Altera Corporation
Resetting Transceiver Channels
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