User guide

• If you use the ATX PLL, set the following configuration settings:
• Under the Master Clock Generation Block Tab
• Enable Include Master Clock Generation Block.
• Turn ON Enable Bonding Clock output ports.
• Turn ON Enable feedback compensation bonding.
• If you use the fPLL, set the following configuration settings:
• Under the PLL Tab
• Set the PLL Feedback type to feedback compensation bonding.
• Under the Master Clock Generation Block Tab
• Turn ON Enable Bonding Clock output ports..
3. Configure the Native PHY IP using the IP Parameter Editor
• Set the Native PHY IP TX Channel bonding mode to either PMA bonding or PMA/PCS
bonding.
4. Create a top level wrapper to connect the PLL IP cores to Native PHY IP core.
• In this case, the PLL IP has tx_bonding_clocks output bus with width [5:0].
• The Native PHY IP has tx_bonding_clocks input bus with width [5:0] multiplied by the number
of channels in a transceiver bank. (six channels in the transceiver bank).
• Unlike the x6/xN bonding mode, for this mode, the PLL should be instantiated multiple times.
(One PLL is required for each transceiver bank that is a part of the bonded group.) Instantiate a
PLL for each transceiver bank used.
• Connect the tx_bonding_clocks output from each PLL to (up to) six channels in the same
transceiver bank.
• Connect the PLL IP core to the PHY IP core by duplicating the output of the PLL[5:0] for the
number of transceiver channels used in the bonding group.
Note:
For this 10-channel example, two ATX PLLs are instantiated. Six channels of the
tx_bonding_clocks on the Native PHY IP core are connected to the first ATX PLL and the
remaining four channels are connected to the second ATX PLL's tx_bonding_clock outputs.
Implementing PLL Cascading
In PLL cascading, the output of the first PLL feeds the input reference clock to the second PLL.
For example, if the input reference clock has a fixed frequency, and the desired data rate was not an
integer multiple of the input reference clock, the first PLL can be used to generate the correct reference
clock frequency. This output is fed as the input reference clock to the second PLL. The second PLL
generates the clock frequency required for the desired data rate.
The transceivers in Arria 10 devices support fPLL to fPLL, fPLL to ATX PLL, or ATX PLL to fPLL
cascading. For OTN and SDI applications, there is a new dedicated clock path for cascading ATX PLL to
fPLL in Arria 10 production silicon..
UG-01143
2015.05.11
Implementing PLL Cascading
3-57
PLLs and Clock Networks
Altera Corporation
Send Feedback