User guide

Figure 3-20: PHY IP Core and PLL IP Core Connection for Multi-Channel x1 Non-Bonded Configuration
Transceiver PLL
Instance (5 GHz)
ATX PLL
Transceiver PLL
Instance (5 GHz)
ATX PLL
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the adjacent transceiver bank.
TX channels placed in the same transceiver bank.
Steps to implement a Multi-Channel x1 Non-Bonded Configuration
1. Choose the PLL IP (ATX PLL, fPLL, or CMU PLL) you want to instantiate in your design and
instantiate the PLL IP.
• Refer to Instantiating the ATX PLL IP Core on page 3-5 or Instantiating CMU PLL IP Core on
page 3-23 or Instantiating the fPLL IP Core on page 3-15 for detailed steps.
2. Configure the PLL IP using the IP Parameter Editor
• For the ATX PLL IP core do not include the Master CGB.
• For the fPLL IP core, set the PLL feedback operation mode to direct.
• For the CMU PLL IP core, specify the reference clock and the data rate. No special configuration
rule is required.
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP TX Channel bonding mode to Non-Bonded.
• Set the number of channels as per your design requirement. In this example, the number of
channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
• The tx_serial_clk output port of the PLL IP represents the high speed serial clock.
• The Native PHY IP has 10 (for this example) tx_serial_clk input ports. Each port corresponds
to the input of the local CGB of the transceiver channel.
• As shown in the figure above, connect the first 6 tx_serial_clk input to the first transceiver PLL
instance.
• Connect the remaining 4 tx_serial_clk input to the second transceiver PLL instance.
UG-01143
2015.05.11
Implementing Multi-Channel x1 Non-Bonded Configuration
3-51
PLLs and Clock Networks
Altera Corporation
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