User guide

FPGA Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver
and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK),
regional (RCLK), and periphery (PCLK) clock networks in the FPGA core. If Global Signal is set to Off, it
does not choose any of the previously mentioned clock networks but chooses directly from the H/V clock
lines (Local Routing).
The transmitter channel forwards a parallel output clock tx_clkout to the FPGA fabric to clock the
transmitter data and control signals. The receiver channel forwards a parallel output clock rx_clkout to
the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric. Based on the
receiver channel configuration, the parallel output clock is recovered from either the receiver serial data or
the rx_clkout clock (in configurations without the rate matcher) or the tx_clkout clock (in configura‐
tions with the rate matcher).
UG-01143
2015.05.11
FPGA Fabric-Transceiver Interface Clocking
3-39
PLLs and Clock Networks
Altera Corporation
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