User guide

Figure 3-7: x1 Clock Lines
CMU or CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
x1 Network
Master
CGB
Master
CGB
ATX PLL1
ATX PLL0
fPLL1
fPLL0
CMU or CDR
x6 Clock Lines
The x6 clock lines route the clock within a transceiver bank. The x6 clock lines are driven by the master
CGB. There are two x6 clock lines per transceiver bank, one for each master CGB. Any channel within a
transceiver bank can be driven by the x6 clock lines.
For bonded configuration mode, the low speed parallel clock output of the master CGB is used and the
local CGB within each channel is bypassed. For non-bonded configurations, the master CGB can also
provide a high speed serial clock output to each channel. In this case, the local CGB within each channel is
not bypassed.
3-32
x6 Clock Lines
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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