User guide

Figure 2-127: Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion
Dx.y K28.0 Dx.y K28.5 K28.0 K28.0tx_parallel_data[19:10]
rx_parallel_data[9:0]
First Skip Cluster Second Skip Cluster
Dx.y K28.5 Dx.y Dx.y K28.0 K28.0tx_parallel_data[9:0]
rx_parallel_data[19:0]
Dx.y K28.0 K28.0 K28.0 Dx.y K28.5 K28.0
Dx.y K28.5 K28.0 K28.0 Dx.y Dx.y K28.0
K28.0
K28.0
The following figure shows the deletion of the 20-bit word D7D8.
Figure 2-128: Rate Match FIFO Becoming Full After Receiving the 20-Bit Word D5D6
D2 D4 D6 D10 D12 xx
D1 D3 D5 D9 D11
xx
rx_parallel_data[19:10]
rx_parallel_data[9:0]
rx_std_rmfifo_full
D2 D4 D6 D8 D10 D12
D1 D3 D5 D7 D9
D11
tx_parallel_data[19:0]
tx_parallel_data[9:0]
The following figure shows the insertion of two skip symbols.
Figure 2-129: Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6
D2 D4 D6 /K30.7/ D8 D10
D1 D3 D5 /K30.7/ D7
D9
rx_parallel_data[19:10]
rx_parallel_data[9:0]
rx_std_rmfifo_empty
D2 D4 D6 D8 D10 D12
D1 D3 D5 D7 D9
D11
tx_parallel_data[19:0]
tx_parallel_data[9:0]
8B/10B Encoder and Decoder
To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX 8B/10B Encoder and
Enable RX 8B/10B Decoder options on the Standard PCS tab in the IP Editor. Qsys allows implementing
the 8B/10B decoder in RX-only mode.
2-302
8B/10B Encoder and Decoder
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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