User guide

You can verify this feature by monitoring rx_parallel_data.
Figure 2-114: Synchronization State Machine Mode when the PCS-PMA Interface Width is 20 Bits
tx_datak
tx_parallel_data
rx_parallel_data
rx_datak
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
11
bc02
0000
00
11
11
00
00
00
02bc
01
11
00
00
00
01
11 00 11 00 11
11
rx_std_wa_patternalign
RX Bit Slip
To use the RX bit slip, select Enable rx_bitslip port, and set the word aligner mode to bit slip. This adds
rx_bitslip as an input control port. An active high edge on rx_bitslip slips one bit at a time, and when
rx_bitslip is toggled, then the word aligner slips one bit at a time on every active high edge. You can
verify this feature by monitoring rx_parallel_data.
The RX bit slip feature is optional and may or may not be enabled.
Figure 2-115: RX Bit Slip in 8-bit Mode
tx_parallel_data = 8'hbc
rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data
01111
bc
00 97 cb e5 f2 79 bc
Figure 2-116: RX Bit Slip in 10-bit Mode
tx_parallel_data = 10'h3bc
000 1de 0ef 277 33b 39d
3bc
01111rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data 3ce 1e7 2f3 379 3bc
2-296
RX Bit Slip
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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