User guide

Figure 2-100: Connection Guidelines for a CPRI PHY Design
PLL IP
Data
Generator
Data
Verifier
Arria 10 Transceiver Native PHY
Reset Controller
pll_powerdown
rx_cdr_refclk
tx_serialclk0
pll_locked
pll_sel
reset
clk
pll_refclk
tx_ready
rx_ready
tx_parallel_data
tx_clkout
rx_parallel_data
rx_clkout
tx_serial_data
rx_serial_data
rx_is_lockedtodata rx_cal_busy tx_cal_busy tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
pll_cal_busy
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Standard PCS Architecture on page 5-37
For more information about Standard PCS architecture
• Arria 10 PMA Architecture on page 5-1
For more information about PMA architecture
• Using PLLs and Clock Networks on page 3-49
For more information about implementing PLLs and clocks
• PLLs on page 3-3
PLL architecture and implementation details
• Resetting Transceiver Channels on page 4-1
Reset controller general information and implementation details
• Standard PCS Ports on page 2-68
Port definitions for the Transceiver Native PHY Standard Datapath
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How to Implement CPRI in Arria 10 Transceivers
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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