User guide

Table 2-164: Channel Width Options for Supported Serial Data Rates
Serial Data Rate
(Mbps)
Channel Width (FPGA-PCS Fabric)
8/10 Bit Width 16/20 Bit Width
8-Bit 16-Bit 16-Bit 32-Bit
614.4 Yes Yes N/A N/A
1228.8 Yes Yes Yes Yes
2457.6 Yes Yes Yes Yes
3072 Yes Yes Yes Yes
4915.2 N/A N/A Yes Yes
6144 N/A N/A Yes Yes
9830.4 N/A N/A N/A Yes
TX PLL Selection for CPRI
Choose a transmitter PLL that fits your required data rate.
Table 2-165: TX PLL Supported Data Rates
ATX and fPLL support the clock bonding feature.
TX PLLs Supported Data Rate (Mbps)
ATX 614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 9830.4
fPLL 614.4, 1228.8, 2457.6, 3072, 4915.2, 6144
CMU 614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 9830.4
Note: Channels that use the CMU PLL cannot be bonded. The CMU PLL that provides the clock can
only drive channels in the transceiver bank where it resides.
Auto-Negotiation
When auto-negotiation is required, the channels initialize at the highest supported frequency and switch
to successively lower data rates if frame synchronization is not achieved. If your design requires auto-
negotiation, choose a base data rate that minimizes the number of PLLs required to generate the clocks
required for data transmission.
By selecting an appropriate base data rate, you can change data rates by changing the local clock
generation block (CGB) divider. If a single base data rate is not possible, you can use an additional PLL to
generate the required data rates.
Table 2-166: Recommended Base Data Rates and Clock Generation Blocks for Available Data Rates
Data Rate (Mbps) Base Data Rate Local CGB Divider
1228.8 9830.4 8
2457.6 9830.4 4
UG-01143
2015.05.11
TX PLL Selection for CPRI
2-269
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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